Memory Cell Column Selection Layout for Dense Bit Line Arrays
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Solution Overview
Problem
The integration of column selection lines in highly integrated memory devices becomes challenging due to interference and spatial constraints, making it difficult to arrange them effectively in memory cell arrays.
Innovation Solution
The implementation of first and second column selection transistors connected in series between a bit line and a local input/output line, with the first transistor controlled by a column selection line in the same direction as the bit line and the second transistor controlled by a row direction word line, allowing column selection lines to be disposed in both column and row directions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If column selection lines are arranged in the memory cell array region, then data transmission between bit lines and input/output lines is enabled, but line density and interference increase making effective arrangement difficult
Solution Approach 1:
The patent introduces a third dimension (vertical stacking) to arrange column selection lines. Instead of placing all column selection lines in the planar memory cell array region, the patent stacks memory cell arrays vertically and places column selection lines in the input/output gate region between stacked layers. This dimensional transition reduces planar line density and interference while maintaining data transmission functionality.
Solution Approach 2:
The patent introduces local input/output lines as intermediary elements between bit lines and main input/output lines. These local lines act as mediators that receive data from selected bit lines through column selection transistors and transfer it to the main input/output infrastructure. This intermediary structure distributes the connection burden and simplifies the overall line arrangement.
2Quantity of substance
If memory cells are highly integrated, then storage capacity increases, but spatial constraints make it difficult to arrange column selection lines
Solution Approach 1:
The patent transitions from two-dimensional planar integration to three-dimensional vertical stacking of memory cell arrays. By stacking arrays in the vertical direction, the patent increases storage capacity without proportionally increasing the planar footprint. This creates additional spatial freedom in the horizontal plane for arranging column selection lines and other peripheral circuits.
Solution Approach 2:
The patent segments the memory device into distinct functional regions: memory cell array regions for storage and an input/output gate region for signal transmission. By separating these functions spatially and vertically, the patent allows high-density memory cell integration while dedicating specific regions (input/output gate region between stacked layers) for column selection line arrangement, thus resolving the spatial conflict.
3Ease of operation
If column selection lines are disposed in the memory cell array region, then bit line selection is enabled, but line density in column direction increases
Solution Approach 1:
The patent introduces local input/output lines as intermediary elements that are connected to bit lines through column selection transistors. These local lines serve as intermediate conduits, allowing bit line selection functionality to be achieved without requiring dense direct connections between column selection lines and main input/output lines. This reduces the effective line density in the column direction while maintaining selection capability.
Solution Approach 2:
The patent moves column selection line arrangements from the horizontal plane within the memory cell array to the vertical dimension in the input/output gate region between stacked memory layers. This vertical displacement reduces the horizontal line density in the column direction while preserving the electrical connection paths for bit line selection through the stacked architecture.
Data Source
AI summary
A memory device including a memory cell array with word lines extending in a first direction and bit lines extending in a second direction, intersecting the first direction; local input/output lines transmitting a potential transmitted through selected bit lines to bit line sense amplifiers; input/output gate regions including first and second column selection transistors connected to the bit lines and corresponding local input/output line; a plurality of first column selection lines connected to gates of first column selection transistors corresponding to first and second bit line groups and extending in the second direction; a second reference column selection line extending in the first direction and connected to gates of second column selection transistors corresponding to the first bit line group, and; and a second complementary column selection line extending in the first direction and connected to gates of second column selection transistors corresponding to the second bit line group.