Memory Cell Column Voltage Control for SRAM Write Margin
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Solution Overview
Problem
Traditional memory devices face write ability issues due to the fighting of P-type and N-type transistors, which can be improved by implementing a voltage control circuit to supply a voltage drop, enhancing write margin and noise margin, and improving stability and reliability.
Innovation Solution
A voltage control circuit with a first and second portion is used to provide intentional voltage drops to memory cells, selectively deactivating the first portion during write operations to suppress P-type transistor strength and maintain a static noise margin without area overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a voltage control circuit is implemented to supply voltage drop and enhance write margin, then write ability and noise margin are improved, but device area increases
Solution Approach 1:
The voltage control circuit is segmented into a first portion and a second portion, where the first portion is selectively deactivated during write operations. This segmentation allows the circuit to provide voltage control during read operations while avoiding area overhead during write operations, resolving the contradiction between reliability improvement and area increase.
Solution Approach 2:
The voltage control circuit employs dynamic activation and deactivation of its first portion based on operational mode (read vs. write). By making the circuit behavior dynamic rather than static, the patent achieves voltage control benefits when needed while minimizing area impact during write operations.
2Reliability
If the first portion of voltage control circuit is activated during write operations, then write margin is enhanced, but P-type transistor strength cannot be suppressed
Solution Approach 1:
The voltage control circuit is divided into two portions with distinct functions: the first portion provides voltage control for read operations, while the second portion suppresses P-type transistor strength during write operations. This segmentation allows both functions to operate independently without interference.
Solution Approach 2:
The voltage control function is extracted into a separate first portion that can be selectively deactivated during write operations. This extraction allows the write operation to proceed without the interfering voltage control that would prevent P-type transistor strength suppression.
3Reliability
If voltage control circuit is added to improve noise margin and stability, then reliability is enhanced, but manufacturing complexity increases
Solution Approach 1:
By segmenting the voltage control circuit into activatable and deactivatable portions, the patent simplifies the manufacturing process. The selective deactivation of the first portion during write operations reduces the overall circuit complexity that needs to be manufactured, while still providing noise margin improvement during read operations.
Data Source
AI summary
A memory circuit includes an array including a plurality of memory cells arranged across a plurality of columns and a plurality of voltage control circuits, each of the plurality of voltage control circuits operatively coupled to the memory cells of a corresponding one of the plurality of columns. Each of the plurality of voltage control circuits includes a first portion configured to provide a first voltage drop in coupling a supply voltage to the memory cells of the corresponding column and a second portion configured to provide a second voltage drop in coupling the supply voltage to the memory cells of the corresponding column. The first voltage drop is substantially smaller than the second voltage drop.