Memory Controller Command Scheduling for Timing Convergence
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Solution Overview
Problem
Existing memory controllers face challenges with increased number of masters, banks, and operating frequency, leading to reduced routability and timing convergency, requiring redesigns.
Innovation Solution
A memory controller that uses a holding unit, generating unit, determining unit, selecting unit, and output unit to synchronize command issuance with a slower clock, ensuring compliance with issuance timing constraints and improving timing convergency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of masters increases, then the memory controller can handle more memory access requests, but the timing convergency of arbiters in a preceding stage deteriorates
Solution Approach 1:
The patent divides the arbitration process into two stages: inter-master arbitration in a preceding stage and inter-bank arbitration in a succeeding stage. By segmenting the arbitration functions, the timing convergency requirements are distributed across different stages, preventing the preceding stage from becoming overly complex when the number of masters increases.
Solution Approach 2:
The patent introduces an intermediary structure where the preceding stage arbitration unit outputs to a succeeding stage arbitration unit. This intermediary stage buffers the timing requirements, allowing the preceding stage to handle more masters without directly impacting the timing convergency of the final arbitration.
2Adaptability or versatility
If the number of banks increases, then the memory controller can handle more memory access requests, but the circuit size increases and timing convergency of arbiters in a succeeding stage deteriorates
Solution Approach 1:
The patent segments the arbitration into inter-master arbitration and inter-bank arbitration performed in different stages. This segmentation prevents the circuit size from increasing proportionally with the number of banks, as the bank arbitration is handled separately in the succeeding stage.
3Speed
If the operating frequency of memory increases, then the memory performance improves, but the design requires changes to maintain timing convergency
Solution Approach 1:
The patent creates a dynamic timing structure where the determination unit operates in synchronization with a clock having a lower frequency than the memory clock. This dynamic frequency separation allows the controller to adapt to different memory frequencies without requiring design changes, as the lower-frequency determination unit provides timing flexibility.
4Adaptability or versatility
If arbitration circuits are added to handle more masters and banks, then the memory controller can handle more requests, but the routability and timing convergency deteriorate
Solution Approach 1:
The patent segments the arbitration functionality into separate units operating at different stages. This segmentation reduces the complexity of individual arbitration circuits, improving routability and timing convergency while maintaining the ability to handle multiple masters and banks.
Data Source
AI summary
A memory controller comprises a holding unit that holds a plurality of memory accesses to a memory that operates with a first clock. The memory controller generates a plurality of command requests for causing the memory to operate based on the plurality of memory accesses; determines, in synchronization with a second clock having a lower frequency than the first clock, whether a plurality of commands corresponding to the plurality of command requests are issuable, based on a constraint on issuance timings that are respectively set for the plurality of commands; selects, in synchronization with the second clock, one command to be issued to the memory from among commands that have been determined by the determining unit to be issuable; and outputs the selected one command to the memory in synchronization with the first clock.