3D Memory Command Address Test Circuit for TSV Failure Detection
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Solution Overview
Problem
Existing semiconductor chips with three-dimensional structures face challenges in detecting failures in the transmission of command addresses through through silicon vias (TSVs) or wire bonding, leading to all memory chips being treated as a failure when a single command address transmission fails.
Innovation Solution
A semiconductor chip design that includes a command address input circuit to generate rising and falling command addresses and a test circuit to latch these addresses, generating detection signals to identify failures by comparing logic levels, allowing for precise detection of command address transmission issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a three-dimensional structure with multiple memory chips is used to increase integration degree and performance, then productivity and performance are improved, but the complexity of detecting transmission failures in command addresses increases
Solution Approach 1:
The command address transmission path is segmented into multiple independent detection paths, with each path having its own detection circuit. This allows individual failure detection in specific through electrodes rather than treating the entire system as failed, enabling precise localization of transmission failures in the three-dimensional memory chip structure.
Solution Approach 2:
A test circuit acts as an intermediary between the command address input circuit and the memory chips. This test circuit includes detection circuits that monitor command addresses during transmission through through electrodes, providing intermediate verification points that enable failure detection without compromising the overall system functionality.
2Reliability
If all memory chips are treated as failed when a command address transmission failure occurs, then reliability is maintained conservatively, but productivity and system availability deteriorate
Solution Approach 1:
The system is segmented into independently detectable units, where failure in one command address transmission path does not necessitate treating all memory chips as failed. The detection circuit identifies specific failed paths, allowing other functional paths to continue operating, thus maintaining system availability while preserving reliability through targeted failure identification.
Solution Approach 2:
Failure detection and treatment are applied locally to specific command address transmission paths rather than globally to the entire memory chip system. When a failure is detected in a particular through electrode or command address path, only that specific path is marked as failed, while other paths continue to operate normally, optimizing system availability.
3Device complexity
If simple transmission without detection is used, then device complexity is reduced, but reliability deteriorates due to undetected failures
Solution Approach 1:
A test circuit serves as an intermediary component that adds detection functionality without significantly increasing overall system complexity. The test circuit includes detection circuits that monitor command addresses during transmission, providing reliable failure detection while maintaining a relatively simple architecture through modular design and integration with existing command address input circuits.
Data Source
AI summary
A semiconductor chip includes a command address input circuit configured to generate a rising command address and a falling command address by receiving an external command address and configured to output the rising command address and the falling command address to a through electrode, and a test circuit configured to generate a detection signal by latching a remaining one of the rising command address and the falling command address as any one of the rising command address and the falling command address and configured to detect a fail in the transmission of the rising command address and the falling command address by detecting the logic level of the detection signal.