Semiconductor Memory Device Common Source Line Architecture
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Solution Overview
Problem
Bipolar Resistive Random Access Memory (RRAM) devices require a bit line and source line for each memory cell, leading to increased memory cell array size due to the need for different data values based on current polarity, resulting in lower memory cell density.
Innovation Solution
A semiconductor memory device design that incorporates first and second active areas on a semiconductor substrate with split word lines, a common source line, and bit lines, allowing adjacent memory cells to share a common source line, thereby reducing the size of the memory cell array and improving cell density through efficient data writing and reading mechanisms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a bit line and source line are provided for each memory cell in bipolar RRAM, then different data values can be written according to current polarity, but the memory cell array size becomes large and memory cell density decreases
Solution Approach 1:
The patent merges the source line function by providing a common source line that is shared by multiple memory cells. Specifically, a first source line is shared by first and second memory cells, and a second source line is shared by third and fourth memory cells. This consolidation reduces the total number of source lines required, thereby decreasing the memory cell array size while maintaining the capability to write different data values through bit line polarity control.
Solution Approach 2:
The common source line serves multiple memory cells simultaneously, making it a universal component that performs the source function for multiple cells. This multi-functionality allows the same source line to be used across different memory cell pairs, reducing redundancy and optimizing the overall array structure.
2Area of stationary object
If a common source line is shared by multiple memory cells, then memory cell density improves and array size reduces, but current path control for exact data storage becomes more challenging
Solution Approach 1:
The patent segments the source line into multiple distinct common source lines, where each common source line is assigned to specific pairs of memory cells. The first source line serves the first and second memory cells, while the second source line serves the third and fourth memory cells. This segmentation ensures that current paths remain well-defined and controlled, preventing interference between adjacent memory cells while maintaining high density through the shared source line architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design enhances memory cell density by ensuring a sufficient current path for data writing and reading, allowing for exact data storage while minimizing the size of the semiconductor memory device and improving operational reliability.
Implementation Method 1
Resistive Random Access Memory (hereinafter, 'RRAM') stores data by varying the resistance of a resistive element. Data may be written to a selected memory cell in an RRAM by applying a predetermined current to the corresponding resistive element.
Data Source
AI summary
There is provided a semiconductor memory device including; first and second active areas formed to extend in a first direction on a semiconductor substrate, first and second split word lines formed in a second direction on the semiconductor substrate, a common source line extending between the first and second active areas in the first direction and coupled to the first and second active areas, a first variable resistance element formed on the first active area between the first and second split word lines, a second variable resistance element formed on the second active area between the first and second split word lines, first and second bit lines extending in the first direction and respectively coupled to the first and second variable resistance elements.