3D Nonvolatile Memory Common Source Via Layout for Noise Suppression
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Solution Overview
Problem
3D nonvolatile memory devices face challenges in suppressing noise and are difficult to design and fabricate, often resulting in unreliable performance.
Innovation Solution
The nonvolatile memory device incorporates a unique structure with a common source plate and peripheral circuit area, utilizing non-penetrating CS vias to connect with the common source plate, reducing noise and enhancing bias voltage capacity without increasing integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 3D nonvolatile memory device architecture is adopted to increase memory cells per unit area, then integration density is improved, but noise suppression becomes more difficult and reliability deteriorates
Solution Approach 1:
The patent divides the peripheral circuit area into a buried area (under the memory cell area) and an exposed area (outside the memory cell area). CS vias are strategically placed in both areas to segment the bias voltage application paths, reducing noise interference in the memory cell region while maintaining high integration density.
Solution Approach 2:
The patent utilizes vertical vias (CS vias) extending through different layers to provide bias voltage to the common source plate. This vertical dimension allows noise reduction without compromising lateral integration density, as the vias can be positioned in both buried and exposed areas of the peripheral circuit region.
2Device complexity
If conventional wiring methods are used to connect peripheral circuits, then device complexity is reduced, but noise interference increases and bias voltage application efficiency deteriorates
Solution Approach 1:
The patent introduces CS vias as intermediary structures to connect the peripheral circuit to the common source plate. These vias serve as dedicated bias voltage pathways that mediate between the control circuit and memory cells, reducing noise coupling while maintaining structural simplicity through standardized via formation processes.
3Ease of manufacture
If bias voltage is applied through conventional means, then manufacturing process simplicity is maintained, but bias voltage application speed and efficiency deteriorates
Solution Approach 1:
The patent forms CS vias in advance during the manufacturing process, preparing dedicated bias voltage pathways before memory cell operation. This preliminary action enables rapid bias voltage application during device operation without compromising manufacturing simplicity, as the vias are integrated into the standard fabrication sequence.
Data Source
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AI summary
A nonvolatile memory device includes; a memory cell area including a cell structure and a common source plate. The memory cell area is mounted on a peripheral circuit area including a buried area covered by the memory cell area and an exposed area uncovered by the memory cell area. A first peripheral circuit (PC) via extending from the exposed area, and a common source (CS) via extending from the common source plate, wherein the first PC via and the CS via are connected by a CS wire disposed outside the cell structure and providing a bias voltage to the common source plate.