Memory Comparator Self-Testing via Tri-State Blocking Circuit
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Solution Overview
Problem
Current memory built-in self-test (MBIST) processes fail to detect faults in the comparator circuit signals of the safety logic, leading to incorrect assertion of the error flag, known as a stuck-at 1 situation, which is not effectively addressed during normal scanning operations.
Innovation Solution
Incorporating a tri-state blocking circuit and a testing control circuit that generates a force signal to block the encoded address and apply a test signal, allowing the comparison circuit to test its own operation, thereby detecting faults in the bit comparator circuits and logic circuit within the safety logic circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If normal MBIST scanning operations are used to test the memory, then the memory array and basic control logic can be tested, but faults in the comparator circuit signals of the safety logic cannot be detected
Solution Approach 1:
The comparison circuit is configured to test its own operation by comparing a force signal applied to the encoded address bus with the memory address. This self-testing capability allows the safety logic circuit to detect faults in its own comparator circuits without requiring separate external test equipment, thereby improving reliability while avoiding additional testing circuit complexity
Solution Approach 2:
The comparison circuit serves dual functions: it performs its normal safety monitoring function during regular memory operations and simultaneously performs self-testing during MBIST operations. This multi-functionality allows the same circuit to both protect against faults and detect its own faults, improving reliability without adding dedicated test circuits
2Reliability
If the encoded address is blocked during testing, then the comparison circuit can be tested with force signals, but the normal address decoding function is interrupted
Solution Approach 1:
The tri-state blocking circuit is activated periodically during MBIST scanning operations to block the encoded address and apply force signals for comparator testing. During normal operations, the blocking circuit is inactive and normal address decoding proceeds uninterrupted. This periodic activation allows fault detection without significantly impacting overall testing efficiency
Solution Approach 2:
The tri-state blocking circuit acts as an intermediary between the encoded address bus and the comparison circuit. It can selectively disconnect the normal encoded address signal and replace it with force signals generated by the testing control circuit, enabling comparator testing while maintaining the integrity of the normal address decoding path when not in test mode
Data Source
AI summary
A decoder decodes a memory address and selectively drives a select line (such as a word line or mux line) of a memory. An encoding circuit encodes the data on select lines to generate an encoded address. The encoded address and the memory address are compared by a comparison circuit to generate a test result signal which is indicative of whether the decoder is operating properly. To test the comparison circuit for proper operation, a subset of an MBIST scan routine causes the encoded address to be blocked from the comparison circuit and a force signal to be applied in its place. A test signal from the scan routine and the force signal are then compared by the comparison circuit, with the test result signal generated from the comparison being indicative of whether the comparison circuit itself is operating properly.