Semiconductor Memory Contact Height Design for Alignment Precision
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Solution Overview
Problem
In the manufacturing of nonvolatile semiconductor memory devices, there is a challenge in maintaining alignment and preventing short-circuits between the bit line and source line contacts, especially as devices are miniaturized, which affects integration level and reliability.
Innovation Solution
The semiconductor memory device design includes a contact structure where the height of the upper surface of the source contact is made lower than the height of the upper surface of the semiconductor layer, allowing for independent positioning of contacts to prevent alignment errors and ensure proper contact alignment, thereby preventing short-circuits and maintaining withstand voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the height of the upper surface of the source contact is made lower than the height of the upper surface of the semiconductor layer, then alignment precision between contacts is improved and short-circuits are prevented, but the manufacturing process complexity increases
Solution Approach 1:
The patent applies dimensionality change by lowering the source contact in the vertical dimension rather than relying solely on horizontal alignment precision. By making the upper surface of the source contact lower than the upper surface of the semiconductor layer, the invention creates a height difference that prevents short-circuits between bit line and source line contacts, thus solving the alignment precision problem through a dimensional approach.
Solution Approach 2:
The contact structure is segmented into different height levels. The source contact is divided into a lower portion that contacts the semiconductor layer and an upper portion that is lower than the semiconductor layer upper surface, while the bit line contact remains at a higher level. This segmentation allows independent positioning and prevents harmful interactions between contacts.
2Productivity
If devices are miniaturized to increase integration level, then productivity and capacity are improved, but alignment precision between contacts deteriorates and short-circuit risk increases
Solution Approach 1:
As devices are miniaturized, horizontal alignment precision becomes increasingly difficult to maintain. The patent compensates for this by utilizing the vertical dimension, creating a height difference between the source contact upper surface and the semiconductor layer upper surface. This dimensional approach maintains reliable contact separation even when lateral dimensions are reduced for higher integration.
Solution Approach 2:
The patent incorporates a design feature that provides a height buffer before short-circuits can occur. By pre-lowering the source contact upper surface relative to the semiconductor layer, the invention creates a safety margin that prevents short-circuits even when alignment variations occur during miniaturized device fabrication.
Data Source
AI summary
According to an embodiment, a semiconductor memory device comprises: a memory string comprising memory cells; and a contact electrically connected to one end of the memory string. The memory string comprises: control gate electrodes stacked above a first semiconductor layer; a second semiconductor layer having one end connected to the first semiconductor layer and having as its longitudinal direction a direction perpendicular to the first semiconductor layer, the second semiconductor layer facing the control gate electrodes; and a charge accumulation layer positioned between the control gate electrode and the second semiconductor layer. The contact has a plate-like shape whose longitudinal direction is a first direction, the contact has its lower surface connected to the first semiconductor layer, and the contact has a height of at least part of its upper surface lower than a height of an upper surface of the second semiconductor layer.