Semiconductor Memory Storage Contact Layout for Lower Resistance
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Solution Overview
Problem
As semiconductor elements become increasingly miniaturized, the complexity of forming multiple wiring lines and buried contacts in highly scaled semiconductor devices increases, making the fabrication process difficult and complex.
Innovation Solution
The semiconductor memory device incorporates a substrate with an active area defined by an element isolation layer, featuring bit lines, storage contacts, and storage pads, where the storage contacts consist of both a lower and upper contact with semiconductor material, and a bit line spacer that does not extend along the upper surface of the lower storage contact, enhancing contact area and reducing contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If semiconductor elements are miniaturized to increase integration density, then integration density improves, but fabrication process complexity increases
Solution Approach 1:
The storage contact is divided into two separate contacts: a lower storage contact extending into the substrate and an upper storage contact extending upward. This segmentation allows each contact to be optimized independently for its specific function, simplifying the overall fabrication process while maintaining high integration density
Solution Approach 2:
The lower storage contact extends in the vertical dimension into the substrate, while the upper storage contact extends upward. This dimensional separation resolves the complexity of forming contacts in highly scaled devices by utilizing different spatial dimensions for different contact functions
2Reliability
If storage contact area is increased to reduce contact resistance, then contact resistance decreases, but device area increases
Solution Approach 1:
Instead of increasing contact area in the horizontal plane, the lower storage contact extends vertically into the substrate. This dimensional transition increases the effective contact area with the active area without increasing the horizontal device footprint, thereby reducing contact resistance while maintaining compact device area
Solution Approach 2:
The lower storage contact is nested within the substrate volume, utilizing the vertical space beneath the bit line structure. This nesting approach increases contact area without consuming additional horizontal device area
Data Source
AI summary
A semiconductor memory device including a substrate including an active area defined by an element isolation layer, a bit line extending in a first direction on the substrate, a storage contact on each of both sides of the bit line and connected to the active area, a storage pad on the storage contact and connected to the storage contact and an information storage portion on the storage pad and connected to the storage pad, wherein the storage contact includes a lower storage contact and an upper storage contact on the lower storage contact, at least a portion of the lower storage contact is in the substrate, an entire upper surface of the lower storage contact is in contact with an entire lower surface of the upper storage contact, and each of the lower storage contact and the upper storage contact includes a semiconductor material may be provided.