Memory Cell Contact Spacers for Charge Leakage Isolation

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Solution Overview

Problem

Non-volatile memory devices face challenges with charge leakage from contacts, which affects programming efficiency, data retention, and device reliability as device dimensions shrink, leading to potential device failure.

Innovation Solution

The implementation of memory devices with contacts having widths ranging from 400 to 900 angstroms, formed in the interlayer dielectric, and the use of spacers to prevent charge leakage by acting as a dielectric barrier, allowing for efficient programming and erasing while reducing space requirements.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If device dimensions are reduced to increase density, then manufacturing throughput and chip size are improved, but charge leakage from contacts to charge storage elements increases

Engineering Contradiction:
Improvemanufacturing throughputVSAvoidcharge leakage
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent divides the contact structure into multiple segments: a contact opening through the interlayer dielectric, a contact plug filling the opening, and a dielectric cap layer covering the contact plug. This segmentation isolates the conductive contact from the charge storage element, preventing charge leakage while maintaining small device dimensions for high-density manufacturing

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a dielectric cap layer as an intermediary barrier between the contact plug and the charge storage element. This dielectric layer acts as a mediator that blocks charge transfer while allowing the contact to maintain its electrical function, thus resolving the charge leakage issue without sacrificing device density

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If contact width is reduced to minimize charge leakage, then charge leakage is improved, but manufacturing precision requirements increase

Engineering Contradiction:
Improvecharge leakage preventionVSAvoidcontact width control
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent applies different quality characteristics to different parts of the contact structure: the contact plug maintains a controlled width for electrical function, while the dielectric cap layer provides additional lateral coverage beyond the contact plug edges. This local differentiation allows the contact plug to be precisely controlled for minimal charge leakage, while the cap layer provides manufacturing tolerance buffer

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The dielectric cap layer is formed beforehand to cover and protect the contact plug, creating a cushioning effect that prevents charge leakage even if contact plug dimensions vary during manufacturing. This pre-established protective layer compensates for potential manufacturing variations

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the reliability and data retention of memory cells by minimizing charge leakage and enabling efficient programming and erasing, while also reducing the physical space needed for memory cell arrays.

Implementation Method 1

charge leakage from a contact to the charge storage element of a memory cell may occur. The charge leakage may occur when electrons travel laterally from the contact through a dielectric layer into the charge storage element

Methodology Applied
Scientific EffectDielectric barrier: Dielectric

Data Source

PatentUS11830942B2Contacts for semiconductor devices
Publication Date: 2023.11.28 INFINEON TECHNOLOGIES LLC
  • US11830942B2 patent drawing
  • US11830942B2 patent drawing
  • US11830942B2 patent drawing

AI summary

In an example embodiment, a method comprises: forming first spacers adjacent to a memory cell formed on a substrate, each of the first spacers being formed in direct contact with the substrate, where forming the memory cell includes forming a control gate electrode and a tunnel oxide layer over the substrate and subsequently etching completely at least the control gate electrode and the tunnel oxide layer that are disposed beyond the memory cell; forming an interlayer dielectric layer over the memory cell and the first spacers; forming a contact hole through the interlayer dielectric layer to at least reach the substrate; subsequent to forming the contact hole, forming a second spacer adjacent to one of the first spacers, where a height of the second spacer is greater than a height of the first spacers, the second spacer substantially contacting the substrate and the interlayer dielectric layer; and forming a contact in the contact hole.