3D Memory Contact Structure for Select Gate Lines
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Solution Overview
Problem
Existing semiconductor storage devices face challenges in achieving an efficient and reliable connection between select gate lines and contacts, leading to increased resistance and potential leakage currents due to the complexity of the three-dimensional memory structure.
Innovation Solution
The semiconductor storage device employs a configuration with stacked conductor layers, memory pillars, and charge storage layers, where the contact is designed to securely connect with the upper surfaces of the select gate lines, reducing the need for a terrace region and allowing for a more direct electrical connection, thereby simplifying the connection process and minimizing resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a three-dimensional memory structure is adopted for high integration, then storage capacity is improved, but connection reliability between select gate lines and contacts deteriorates
Solution Approach 1:
The patent transitions from planar contact connections to three-dimensional contact structures that extend vertically through multiple conductor layers. Contacts are formed as stacked structures connecting to upper surfaces of select gate lines at different heights, utilizing the vertical dimension to improve connection reliability while maintaining high integration density.
Solution Approach 2:
The contact structure is designed as a nested configuration where multiple conductor layers are stacked within the contact region. The contact connects to select gate lines at different vertical levels, with inner conductor layers nested within outer ones, creating a multi-level connection system that enhances reliability without increasing planar footprint.
2Quantity of substance
If stacked wiring layers are implemented, then integration density is improved, but connection resistance increases
Solution Approach 1:
The patent utilizes vertical stacking of conductor layers to create multiple parallel conduction paths. By extending contacts vertically to connect with upper surfaces of select gate lines at different heights, the design creates additional conduction pathways that reduce overall connection resistance while maintaining high integration density in the vertical dimension.
Solution Approach 2:
Multiple conductor layers are merged into a unified contact structure that simultaneously connects to multiple select gate lines. The stacked wiring layers are combined within the contact region to form integrated conduction paths, reducing total resistance by providing parallel current flow routes through the stacked configuration.
3Quantity of substance
If complex three-dimensional structure is used, then storage capacity is improved, but manufacturing complexity increases
Solution Approach 1:
The patent employs preliminary patterning actions where conductor layers and contact regions are pre-formed in specific stacked configurations before final contact formation. The stacked wiring structure is prepared in advance with predetermined layer arrangements, simplifying subsequent contact fabrication processes and reducing overall manufacturing complexity despite the three-dimensional structure.
Solution Approach 2:
The complex three-dimensional structure is segmented into discrete stacked conductor layers and contact regions that can be fabricated independently and then integrated. Each conductor layer and contact segment is formed as a separate unit with defined geometry, allowing modular manufacturing processes that reduce complexity compared to forming the entire structure in a single complex step.
Data Source
AI summary
A semiconductor memory device includes a plurality of first conductor layers that are stacked in a first direction; a first pillar including a first semiconductor layer and extending through the first conductor layers in the first direction; a first charge storage layer that is provided between the first conductor layers and the first semiconductor layer; a plurality of second conductor layers that are stacked in the first direction above an uppermost conductor layer of the first conductor layers; a second pillar including a second semiconductor layer and extending through the second conductor layers in the first direction, the second semiconductor layer electrically connected to the first semiconductor layer; and a conductor pillar or film extending in the first direction through the second conductor layers other than a lowermost layer of the second conductor layers and being in contact with a respective upper surface of each of the second conductor layers.