Memory Control Circuit Batch Verification for Data Rewriting
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Solution Overview
Problem
Existing memory control circuits face inefficiencies in data rewriting due to frequent mode switching between write and verification modes, leading to increased processing time, especially when multiple data points are unverified, and existing techniques like Maruyama et al.'s method require unnecessary switching operations and overhead time.
Innovation Solution
A memory control circuit with a writable/readable memory, a comparison unit, a comparison result storage unit, and a control unit that collectively handles unverified data for retry processing, reducing the need for frequent mode switching by performing verification and retry processing in batches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If verification processing is performed immediately after write processing for each data point, then data writing reliability is improved, but processing time increases due to frequent mode switching
Solution Approach 1:
The patent segments the verification process by dividing multiple data points into groups. Instead of verifying each data point individually immediately after writing, the system writes multiple data points first and then performs verification in batches. This segmentation allows the system to maintain reliability through verification while reducing the overhead of frequent mode switching between write and verify operations.
Solution Approach 2:
The patent applies preliminary action by performing the write operation for multiple data points before initiating verification processing. The system prepares and writes data to the memory in advance, then switches to verification mode only after the write batch is complete. This approach ensures data is written reliably while minimizing the time spent in verification mode, thus reducing overall processing time.
2Reliability
If retry processing is performed for each unverified data point with mode switching, then data integrity is improved, but processing speed deteriorates
Solution Approach 1:
The patent segments retry processing by identifying and grouping unverified data points together. Instead of immediately retrying each failed verification individually with mode switching, the system collects all unverified data points and processes them as a batch. This segmentation maintains data integrity by ensuring all unverified points are addressed while improving processing speed by reducing the frequency of mode transitions.
Solution Approach 2:
The patent merges multiple retry operations into a single batched processing step. When verification fails for multiple data points, the system combines these retry operations and executes them together in one verification mode pass rather than switching modes repeatedly for each individual retry. This merging approach preserves data integrity while significantly improving processing speed by eliminating redundant mode switching overhead.
3Measurement precision
If mode switching between write and verification modes is performed frequently, then processing accuracy is improved, but overhead time increases
Solution Approach 1:
The patent implements periodic action by establishing a rhythm of operations: a write phase followed by a verification phase, repeated in periodic cycles. Instead of switching modes after every single data point, the system performs writes for a batch of data points, then switches to verification mode for that batch, and repeats this periodic pattern. This approach maintains processing accuracy by ensuring regular verification while reducing overhead time by minimizing the frequency of mode transitions.
Data Source
AI summary
A memory control circuit according to an embodiment of the present invention includes: a writable/readable memory; a comparison unit comparing write data to write in the memory with read data that is read from a memory address where the write data is written; a comparison result storage unit storing a comparison result compared by the comparison unit in association with the memory address; and a control unit controlling retry processing of rewriting the write data to the memory address determined to be unverified based on the stored comparison result.