Non-Volatile Memory Control Block Grouping for Voltage Stress Reduction
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Solution Overview
Problem
The high programming voltage in EEPROM memories poses challenges for fabrication technology and reliability due to increased risks of transistor breakdown and premature aging, and existing solutions like 'split voltage' complicate the fabrication process and memory plane uniformity.
Innovation Solution
A non-volatile memory device architecture with grouped control elements that reduce the surface area and uniformity rupture, using a 'split-voltage' type programming with a configuration where control elements are grouped to share connections, allowing for reduced voltage stress and selective source line powering to prevent spurious erasing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If high programming voltage (13 volts) is used for EEPROM memories, then programming operation is achieved, but transistor breakdown and premature aging risks increase
Solution Approach 1:
The high programming voltage is segmented into two separate voltages: a first voltage (e.g., 4 volts) applied to word lines and a second voltage (e.g., -9 volts) applied to bit lines. This segmentation allows the total voltage difference across the memory cell to reach the required 13 volts for programming while keeping individual line voltages within safe operating limits, thus preventing transistor breakdown and premature aging.
2Reliability
If split voltage approach is used to reduce voltage constraint, then transistor reliability improves, but fabrication process complexity increases
Solution Approach 1:
The memory device is segmented into two distinct voltage domains: word lines receive a first voltage while bit lines receive a second voltage. This segmentation is implemented through separate voltage generation circuits and distribution networks, allowing independent control of each voltage domain. The segmentation enables the use of standard fabrication processes while achieving the desired voltage separation for improved reliability.
3Ease of operation
If control elements are distributed over every other column, then control function is achieved, but memory plane uniformity is ruptured
Solution Approach 1:
Multiple control elements that were previously distributed across different columns are merged into concentrated control blocks located at the edges of memory blocks. This merging consolidates control functions into specific regions, eliminating the periodic interruptions in memory plane uniformity while maintaining full control capability. The control blocks can manage multiple memory words efficiently, reducing the need for distributed control elements.
4Stability of the object's composition
If inactive structures are added along memory block edges to reduce behavior variations, then uniformity is improved, but surface area occupied increases
Solution Approach 1:
The control elements that would traditionally require inactive structures around them are merged into compact control blocks positioned at the edges of memory blocks. This merging eliminates the need for surrounding inactive structures, as the control blocks themselves are positioned to minimize disruption to memory plane uniformity. The control blocks serve multiple control functions while occupying minimal space, thereby reducing the overall surface area compared to distributed control with inactive structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a more compact and reliable non-volatile memory device with reduced risk of transistor breakdown and improved uniformity, maintaining performance while simplifying the fabrication process.
Implementation Method 1
The programming or the erasing of a floating-gate transistor consists of the injection or the extraction of the electrical charges into or from the gate of the transistor by tunnel effect (Fowler-Nordheim effect) by means of a high voltage Vpp
Data Source
AI summary
A non-volatile memory device includes a substrate, a plurality of memory words, a control block, a first electrically-conducting link, and a plurality of second electrically-conducting links. The substrate includes a substantially planar surface. The memory words include B memory words disposed at the substantially planar surface. The control block includes B control elements disposed at the substantially planar surface. The first electrically-conducting link is disposed in a first plane parallel to the substantially planar surface. The first electrically-conducting link connects one of the B control elements to a memory word of the memory words. The plurality of second electrically-conducting links includes B-1 second electrically-conducting links respectively connecting B-1 remaining control elements to B-1 corresponding memory words of the plurality of memory words. The B-1 second electrically-conducting links are disposed above the first plane and physically extend at least partially over at least two memory words of the memory words.