Memory Control Circuit Unit Adaptive Voltage Level Decoding

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Solution Overview

Problem

As memory devices age, the default read voltage level used for data retrieval becomes less effective, leading to increased errors that exceed the error correction capability, necessitating an improvement in decoding efficiency.

Innovation Solution

A method involving multiple voltage levels for reading memory cells, including hard-decision, soft-decision, and test voltage levels to obtain hard-bit and soft-bit information, with estimating parameters used to update the default hard-decision voltage level, enhancing decoding efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the default read voltage level is used for reading data from memory cells, then the reading operation is simple and fast, but the decoding capability deteriorates as memory devices age and usage time increases

Engineering Contradiction:
Improvedecoding capabilityVSAvoidreading operation complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The system performs preliminary actions by first attempting hard-decoding with the default voltage level, then progressively transitioning to soft-decoding with multiple voltage levels only when hard-decoding fails. This preliminary action approach maintains simplicity for normal operations while preparing advanced decoding capabilities for when they are needed, resolving the contradiction between reliability and complexity.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system changes the voltage level parameter dynamically based on decoding needs. It starts with a single default voltage level for simple readings, then transitions to multiple voltage levels (different soft-decision voltage levels) when error correction is needed. This parameter change allows the system to adapt to aging memory devices while managing operational complexity.

Inventive Principle:
Principle #35Parameter changes

2Productivity

If multiple voltage levels are used for reading memory cells to improve decoding capability, then the decoding efficiency improves, but the reading operation time and complexity increase

Engineering Contradiction:
Improvedecoding efficiencyVSAvoidreading operation time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The decoding process is segmented into distinct stages: hard-decoding stage using default voltage level, and soft-decoding stage using multiple voltage levels. The system only proceeds to the more time-consuming soft-decoding stage when hard-decoding fails, thus achieving high decoding efficiency for most cases while minimizing the time penalty for the enhanced capability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system applies partial action by using only the necessary number of voltage levels based on decoding requirements. It doesn't always use all multiple voltage levels, but rather applies them partially only when needed, thereby improving decoding efficiency without always incurring the full time cost of complex multi-voltage readings.

Inventive Principle:
Principle #16Partial or excessive action

3Reliability

If the default read voltage level is used, then the reading operation is fast, but the error correction capability becomes insufficient as memory devices age

Engineering Contradiction:
Improveerror correction capabilityVSAvoidreading speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The system dynamically adjusts the reading operation based on real-time feedback from decoding attempts. It starts with fast default voltage level readings, then dynamically transitions to slower but more reliable multi-voltage soft-decoding only when errors are detected. This dynamic approach maintains high reading speed for good data while ensuring error correction capability for degraded memory devices.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS9952926B2Decoding method, memory storage device and memory control circuit unit
Publication Date: 2018.04.24 SHENZHEN EPOSTAR ELECTRONICS LTD
  • US9952926B2 patent drawing
  • US9952926B2 patent drawing
  • US9952926B2 patent drawing

AI summary

A decoding method, a memory storage device and a memory control circuit unit are provided. The decoding method includes: reading memory cells based on a default hard-decision voltage level and decoding the obtained hard-bit information; if the decoding fails, reading the memory cells based on default soft-decision voltage levels and then decoding the obtained soft-bit information; if the decoding still fails, reading the memory cells based on first test voltage levels to obtain first soft-bit information and reading the memory cells based on second test voltage levels to obtain second soft-bit information; obtaining a first estimating parameter and a second estimating parameter according to the first soft-bit information and the second soft-bit information, respectively; and updating the default hard-decision voltage level according to the first estimating parameter and the second estimating parameter. As a result, a decoding efficiency can be improved.