Memory Control Circuitry Timing Offset for Disturbance Mitigation
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Solution Overview
Problem
Existing usage-based disturbance mitigation techniques in memory devices have limited time for error corrections and other tasks due to the back-to-back execution of internal read and write operations, leading to increased precharge times and degraded performance.
Innovation Solution
The control circuitry generates internal read and write commands based on separate external commands, allowing for a timing offset between the two operations to perform error corrections and other tasks before the internal write operation, thereby reducing external precharge time and improving overall performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If internal read and write operations are executed back-to-back, then device complexity is reduced, but time for error corrections and other tasks is insufficient
Solution Approach 1:
The patent segments the internal read and write operations by associating them with different external commands (first command for read, second command for write). This allows the operations to be separated in time by the command timing offset, providing sufficient time for error corrections and other tasks between the read and write operations while maintaining relatively simple device complexity.
2Productivity
If internal read and write operations are executed back-to-back, then productivity is improved, but external precharge time increases
Solution Approach 1:
The patent performs the internal read operation in advance by associating it with an earlier first external command, before the second external command that triggers the write operation. This preliminary action allows the read to complete with sufficient time for error corrections before the write operation begins, thereby reducing the external precharge time required between read and write operations.
3Device complexity
If internal read and write operations are executed back-to-back, then device complexity is reduced, but reliability is compromised
Solution Approach 1:
The patent introduces timing offset between the first and second external commands as an intermediary element. This timing offset serves as a mediator that provides sufficient time for error corrections and other tasks between the internal read and write operations, thereby improving reliability without significantly increasing device complexity.
Data Source
AI summary
Apparatuses and methods for scheduling aspects of usage-based disturbance mitigation based on different external commands are described. An apparatus comprises a memory device, which has at least one bank comprising memory cells. A subset of the memory cells is configured to store data associated with usage-based disturbance. The apparatus includes circuitry configured to mitigate usage-based disturbance within the bank. The memory device is configured to receive, from a memory controller, two commands that are separated in time by a timing offset. The memory device is configured to generate an internal read command based on the first command to cause the memory device to read the data from the subset of the memory cells. The memory device is configured to generate an internal write command based on the second command to cause the memory device to write modified data generated by the circuitry to the subset of the memory cells.