Memory Control Circuit Using RNN Scheduling for Variable Access Times
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Solution Overview
Problem
The varying memory access times due to different memory specifications, system architecture, and clock frequencies in electronic circuits lead to inefficiencies in memory control, necessitating improved estimation and optimization of memory access efficiency.
Innovation Solution
A memory control circuit utilizing recurrent neural networks to monitor and encode operation records into feature vectors, predict optimal terminal combinations, and schedule tasks to enhance efficiency, incorporating idle state monitoring for improved accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory access is controlled using traditional fixed scheduling methods, then the control logic is simple, but the memory access efficiency is low due to varying access times for different modules
Solution Approach 1:
The patent replaces traditional mechanical scheduling methods with an artificial neural network-based prediction system. The ANNN predicts memory access times by learning from historical access patterns, replacing fixed scheduling logic with adaptive intelligence that optimizes memory access efficiency without requiring complex manual scheduling rules
Solution Approach 2:
The memory control element performs self-optimization by using its own historical access records to train the ANNN. The system automatically learns from its operational data and adjusts scheduling decisions without external intervention, enabling continuous improvement of access efficiency while maintaining simple control architecture
2Adaptability or versatility
If the memory control element adapts to different module characteristics, then the access efficiency improves, but the estimation complexity increases
Solution Approach 1:
The patent changes the parameter representation by encoding module characteristics and access patterns into numerical features that the ANNN can process. Instead of complex qualitative analysis, the system uses quantitative parameters from historical access records to predict future access times, simplifying the estimation process while maintaining high adaptability
Solution Approach 2:
The ANNN acts as an intermediary between raw access records and scheduling decisions. It processes historical access data and module characteristics through learned patterns to generate accurate access time predictions, bridging the gap between complex module variations and simple scheduling control
3Measurement precision
If comprehensive monitoring of operation records is performed, then the prediction accuracy improves, but the data processing load increases
Solution Approach 1:
The patent extracts only the essential features from comprehensive operation records that are most relevant to access time prediction. Instead of processing all raw data, the system identifies and extracts key parameters such as access patterns, module types, and timing information, reducing processing load while maintaining high prediction accuracy
Solution Approach 2:
The system performs monitoring at a level that provides sufficient accuracy without excessive processing. By using the ANNN to learn from representative samples of operation records and predict future access times, the system achieves high accuracy while avoiding the need to process every single access event in detail
Data Source
AI summary
A memory control circuit includes a plurality of main terminal circuits, a monitoring unit, an arithmetic unit, and a memory controller. The main terminal circuits output a plurality of control commands. The monitoring unit generates an operation record based on each of the control commands. The arithmetic unit includes a recurrent neural network module. The arithmetic unit generates a corresponding first feature vector based on the operation record and generates a plurality of second feature vectors based on the first feature vectors corresponding to a plurality of candidate combinations. The recurrent neural network module obtains estimated efficiency information based on the second feature vectors and selects a candidate combination corresponding to one piece of the estimated efficiency information as a selected main terminal combination. The memory controller is configured to execute the control command corresponding to each main terminal circuit in the selected main terminal combination for a memory.