Memory Controller PCBA Testing via ATPG Vectors
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Solution Overview
Problem
Conventional testing methods for memory sub-system controllers at the printed circuit board assembly level are inefficient, relying on redundant firmware development and experiencing high execution times, leading to increased manufacturing costs and reduced test coverage.
Innovation Solution
An in-circuit test device is used to reuse Automated Test Pattern Generation (ATPG) test vectors, which are applied to dual-purpose test pins on the memory sub-system controller, allowing for comprehensive testing and reducing redundant efforts by leveraging existing ATPG vectors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional firmware-based testing is used at the PCBA level, then the controller can be tested for functionality, but the execution time is 1-2 orders of magnitude higher than hardware operations and test coverage is reduced
Solution Approach 1:
The patent replaces firmware-based testing (software execution) with hardware-based ATPG testing. The controller is configured to operate in a test mode where ATPG test vectors are applied directly to test input pins, and responses are captured through test output pins, bypassing the firmware execution path entirely. This substitution of testing mechanism reduces execution time by 1-2 orders of magnitude while improving test coverage.
2Reliability
If firmware is developed to test the controller, then the controller functionality can be verified, but redundant manual development is required and NRE costs increase
Solution Approach 1:
The patent extracts the testing functionality from the firmware domain and places it in the hardware domain. The controller includes dedicated test input pins and test output pins that are separate from the normal operational interfaces. ATPG test vectors are applied directly to these hardware test pins, and responses are captured through the same hardware path, eliminating the need for firmware-based testing and its associated development complexity and NRE costs.
3Ease of operation
If the controller executes firmware to test itself, then testing can be performed, but there is an inherent loss in test coverage
Solution Approach 1:
The patent replaces the firmware-based self-testing mechanism with a hardware-based ATPG testing approach. The controller is configured with test mode logic that, when activated, routes test vectors applied to test input pins directly through the hardware logic under test and captures responses at test output pins. This hardware-based approach provides complete visibility into the controller's internal logic states and eliminates the inherent test coverage losses associated with firmware execution.
Data Source
AI summary
A system comprises a memory sub-system controller mounted to a printed circuit board (PCB) and an in-circuit test (ICT) device. The memory sub-system controller has test points on the PCB comprising stimulus points and observation points. The ICT device connects to the test points of the controller. The ICT device converts automated test pattern generation (ATPG) input test vectors to test signals. A first set of pin drivers of the ICT device applies the test signals to the stimulus points of the controller and a second set of pin drivers of the ICT device read output signals output at the observation points of the controller. A comparator of the ICT device compares the output signals with output test vectors. The comparator provides test result data comprising a result of the comparison.