Memory Controller Bit Correction via Multiple Read Voltages
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Solution Overview
Problem
Current error correction codes (ECC) in memory storage devices are limited in their ability to correct errors beyond their correction capacity, leading to uncorrectable data errors.
Innovation Solution
The system employs multiple read voltages to identify and correct errors by comparing bit values obtained at different voltages, using a bit value corrector to generate corrected data and iteratively apply ECC procedures until successful correction is achieved.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional ECC procedures are used to correct errors in stored data, then data integrity is maintained within the correction capacity of the ECC, but errors exceeding the correction capacity cannot be fixed
Solution Approach 1:
The system performs preliminary reads of the storage elements at multiple different read voltages before the ECC correction process. By obtaining multiple candidate data sets in advance at different voltage levels, the system creates a pool of potential correct values that can be used to correct errors exceeding the original ECC capacity, allowing the ECC to successfully correct more errors than its standard capacity would allow
Solution Approach 2:
The invention changes the read voltage parameter to obtain different data representations of the same storage elements. By varying the read voltage across multiple levels and comparing the resulting bit patterns, the system identifies bits that flip between different voltage readings as likely erroneous bits, enabling correction beyond the original ECC capacity
2Adaptability or versatility
If multiple read voltages are used to correct errors, then the ability to correct errors exceeds the original ECC capacity, but the complexity of the read and correction process increases
Solution Approach 1:
The system performs preliminary reads of the storage elements at multiple different read voltages before the ECC correction process. By obtaining multiple candidate data sets in advance at different voltage levels, the system creates a pool of potential correct values that can be used to correct errors exceeding the original ECC capacity, allowing the ECC to successfully correct more errors than its standard capacity would allow
Solution Approach 2:
The system uses feedback from comparing bit patterns obtained at different read voltages to identify erroneous bits. By analyzing which bits flip between different voltage readings, the system generates a feedback signal that indicates which bits are likely incorrect, guiding the ECC correction process to focus on these specific bits and reducing overall correction complexity
3Measurement precision
If multiple read voltages are applied to storage elements, then bit errors can be identified through comparison, but additional read operations and processing time are required
Solution Approach 1:
The system performs preliminary reads of the storage elements at multiple different read voltages before the ECC correction process. By obtaining multiple candidate data sets in advance at different voltage levels, the system creates a pool of potential correct values that can be used to correct errors exceeding the original ECC capacity, allowing the ECC to successfully correct more errors than its standard capacity would allow
Solution Approach 2:
The system applies different read voltages selectively to identify bits with uncertain or erroneous values. Rather than uniformly processing all bits, the method focuses the additional read operations and comparison logic specifically on bits that flip between different voltage readings, optimizing the balance between measurement precision and time consumption
Data Source
AI summary
A data storage device includes a memory including a group of storage elements. The memory is configured to read the group of the storage elements. A controller is coupled to the memory. The controller is configured to, in response to a first error correction code (ECC) procedure determining that a first plurality of bit values obtained using a first read voltage to read the group of storage elements is uncorrectable, instruct the memory to read the group of the storage elements using a second read voltage to obtain a second plurality of bit values. The controller is further configured to compare the first plurality of bit values with the second plurality of bit values to identify a first set of bits having different values in the first plurality of bit values as compared to the second plurality of bit values and to change one or more values of the first plurality of bit values for one or more bits in the first set of bits to generate a first plurality of corrected bit values.


