Memory Controller Clock Training via Voltage Feedback
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Solution Overview
Problem
As DDR memory speeds increase, there is a risk that clock settings during power up will not be adequate for high frequency operation, leading to inefficiencies and risks in memory subsystems, particularly in registered DIMM systems with multiple ranks and channels.
Innovation Solution
A mechanism is introduced where a memory device, such as a DRAM, sends a voltage response signal back to the memory controller through data lines, allowing the controller to analyze the clock signal quality and adjust termination settings accordingly, ensuring effective operation across varying frequencies and raw card designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If clock signal frequency is rapidly increased to desired high frequency during power up, then memory operation speed is improved, but system reliability deteriorates due to risk of inadequate clock settings and on-die termination issues
Solution Approach 1:
The patent applies preliminary action by performing termination training and calibration before the memory device operates at high clock frequencies. The system first establishes appropriate on-die termination (ODT) settings through a training sequence, then proceeds to high-speed operation. This ensures that when the clock frequency is rapidly increased, the termination settings are already optimized, preventing reliability issues while maintaining speed improvements.
Solution Approach 2:
The patent implements feedback mechanisms where the memory device sends voltage response signals back to the memory controller during the training phase. The controller analyzes these responses and adjusts ODT settings accordingly. This closed-loop feedback ensures that termination settings are optimized for the specific hardware configuration before high-speed operation begins, resolving the contradiction between speed and reliability.
2Adaptability or versatility
If multiple default ODT settings are added per raw card, then adaptability to different frequencies and topologies is improved, but device complexity increases
Solution Approach 1:
The patent applies dynamics by making ODT settings changeable and adaptive rather than static. Instead of hardcoding multiple settings, the system dynamically determines and adjusts ODT values during the training phase based on actual voltage response measurements. This allows the system to adapt to different frequencies and topologies without requiring pre-configured settings for each scenario, maintaining simplicity while achieving versatility.
Solution Approach 2:
The patent utilizes parameter changes by adjusting ODT resistance values based on measured voltage responses during training. The system varies termination parameters dynamically to optimize performance for different operating conditions. This approach provides adaptability across frequencies and topologies by changing parameters in response to actual measurements rather than relying on pre-defined settings for each scenario.
3Productivity
If clock settings are optimized for high frequency operation from power up, then productivity is improved, but risk of system failure increases due to inadequate settings for varying ODT conditions
Solution Approach 1:
The patent resolves this contradiction by performing preliminary training and calibration actions before enabling high-frequency operation. The system first establishes optimal clock and termination settings through a training sequence that measures voltage responses, then proceeds to high-speed productivity-critical operations. This preliminary preparation eliminates the risk of system failure while maintaining high productivity during normal operation.
Solution Approach 2:
The patent applies the skipping principle by rapidly transitioning through the training phase to reach high-frequency operation. Once optimal settings are established through brief training, the system quickly moves to productive high-speed operation. This minimizes the time spent in the low-frequency training state while ensuring reliability is established before productivity-critical operations begin, effectively skipping directly to optimal performance after brief calibration.
Data Source
AI summary
A method, apparatus and system. The method includes: performing one or more training iterations to tune a target clock signal frequency to be applied at a memory device, each of the one or more training iterations including: causing a modified clock signal frequency to be applied at the memory device; and decoding a quality feedback message from the memory device including an indication of a performance of the clock signal frequency at the memory device; and in response to a determination that the performance of the clock signal frequency falls within a target performance range of the memory device and that the clock signal frequency is below the target clock signal frequency, performing a subsequent training iteration of the one or more training iterations, and otherwise causing application at the memory device, during a memory operation, of a highest clock signal frequency corresponding to a training iteration for which performance of the clock signal was within the target performance range.