Memory Controller Error Position Extraction for Flash Data Reliability

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Solution Overview

Problem

As the number of bits stored per memory cell increases in flash memory devices, the read margin of each memory cell decreases, leading to an increase in data storage errors.

Innovation Solution

A method for improving the reliability of data storage in flash memory devices by extracting error position information from data stored in a memory device, refining read data based on this information, and performing soft decision decoding to generate corrected data.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the number of bits stored per memory cell is increased to increase storage capacity, then the storage capacity increases, but the read margin decreases and error rate increases

Engineering Contradiction:
Improvestorage capacityVSAvoiddata storage reliability
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent segments the error correction process into multiple stages: first error correction using ECC, then soft decision decoding, and finally a second error correction stage. This multi-stage segmentation allows the system to handle higher error rates associated with multi-bit per cell storage without requiring a single overly complex error correction mechanism.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary error correction using ECC before proceeding to soft decision decoding. This preliminary action reduces the error burden on subsequent decoding stages, enabling the system to maintain reliability even with increased storage density that produces higher error rates.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If advanced error correction techniques are used to reduce errors in high-density storage, then data reliability improves, but device complexity increases

Engineering Contradiction:
Improvedata storage reliabilityVSAvoiderror correction complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The error correction functionality is segmented across multiple independent stages: ECC engine for first correction, soft decision decoder for intermediate processing, and a second error correction stage. This segmentation allows each component to be optimized independently and prevents any single component from becoming excessively complex.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The soft decision decoder acts as an intermediary between the first ECC stage and the second error correction stage. It processes the data with intermediate complexity, transforming the error patterns into a form that is more amenable to final correction without requiring either endpoint to handle the full complexity alone.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If multiple error correction stages are implemented to correct errors in high-density storage, then error correction capability improves, but processing time increases

Engineering Contradiction:
Improveerror correction capabilityVSAvoiddata processing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The error correction is structured as periodic staged operations: first ECC correction, then soft decision decoding, and finally second error correction. This periodic multi-stage approach allows the system to process errors systematically at different levels of complexity rather than attempting single-pass correction, improving overall capability while managing time through structured repetition.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The first ECC correction stage performs preliminary error correction before the data proceeds to soft decision decoding. This preliminary action reduces the number of errors that need to be handled in subsequent stages, decreasing the total processing time required for complete error correction despite the multiple stages.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentEP4152333B1Operation method of memory controller configured to control memory device
Publication Date: 2025.02.19 SAMSUNG ELECTRONICS CO LTD
  • EP4152333B1 patent drawingFigure 1
  • EP4152333B1 patent drawingFigure 2
  • EP4152333B1 patent drawingFigure 3

AI summary

Disclosed herein are operation methods of a memory controller which controls a memory device. The method includes storing write data in a first area of the memory device, extracting first error position information indicating a position of at least one error included in data stored in the first area, storing the first error position information in a second area of the memory device, reading read data from the first area of the memory device, reading the first error position information from the second area of the memory device, refining the read data based on the first error position information to generate refined data, performing soft decision decoding based on the refined data to generate corrected data, and outputting the corrected data.