Memory Controller Parity Recovery for Sudden Power-Off Data Integrity
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Solution Overview
Problem
Current memory systems face challenges in efficiently processing and storing multi-bit data due to operational complexity and performance degradation, particularly during sudden power-offs and errors, which can lead to incomplete programming and data loss.
Innovation Solution
A memory system comprising a first memory group for multi-bit data and a second memory group for single-bit data, with a program operation controller that generates parity, performs verification, and recovers data using parity information, ensuring data integrity and completeness even after power resumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-bit data is programmed in a single memory group, then storage capacity is improved, but data reliability deteriorates due to incomplete programming during power-offs
Solution Approach 1:
The patent divides multi-bit data into multiple single-bit data groups and stores them in separate memory groups. This segmentation allows individual bits to be programmed and verified independently, so that if power is lost during programming, already-programmed bits remain intact and can be recovered without affecting other bits.
Solution Approach 2:
The patent performs preliminary programming of individual bits within multi-bit data before final assembly. By programming and verifying each bit separately in advance, the system ensures that data integrity is maintained even if power is interrupted during the overall programming process, as each bit has already been successfully programmed and verified.
2Productivity
If multi-bit data is programmed in a single memory group, then programming speed is improved, but operational complexity increases due to error handling
Solution Approach 1:
The patent segments multi-bit data into individual bits stored in separate memory groups, which simplifies error handling. Instead of managing complex errors in multi-bit programming, the system only needs to handle single-bit operations, reducing the complexity of error detection, verification, and recovery procedures.
Solution Approach 2:
The patent implements verification operations after programming each bit to provide feedback on programming status. This feedback mechanism allows the system to detect programming completion or errors immediately and take appropriate actions, simplifying the overall error handling process compared to verifying multi-bit data as a single unit.
3Reliability
If parity information is stored with multi-bit data, then data recovery is improved, but storage efficiency deteriorates
Solution Approach 1:
The patent segments data into individual bits stored in separate memory groups, which eliminates the need for additional parity information. Each bit's separate storage and verification inherently provide error detection and recovery capabilities without requiring extra storage space for parity bits, thus maintaining storage efficiency while improving data recovery capability.
Data Source
AI summary
A memory device includes a first memory group including plural first non-volatile memory cells capable of storing multi-bit data, and a second memory group including plural second non-volatile memory cells capable of storing single-bit data. A program operation controller builds the multi-bit data based on data inputted from an external device, performs a logical operation regarding partial data among the multi-bit data to generate a parity, programs the parity in the second memory group after programming the partial data in the first memory group, perform a verification operation regarding the partial data after a sudden power-off (SPO) occurs, recovers the partial data based on the parity and a result of the verification operation, and programs recovered partial data in the first memory group.