Memory Controller Read Sequencing with Skipped Plane Status Checks
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Solution Overview
Problem
Existing memory controllers for nonvolatile memory devices inefficiently manage read operations by unnecessarily checking status information of memory planes, leading to increased operational time and power consumption.
Innovation Solution
A memory controller that predicts the readiness of memory planes based on elapsed time since a read command is issued, skipping status read commands when a threshold time is exceeded, and directly transmitting memory access commands to improve operational speed and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If status read commands are issued to check memory plane readiness, then operational reliability is improved, but operational time and power consumption increase
Solution Approach 1:
The memory controller performs preliminary actions by issuing the memory access command before confirming the memory plane is ready. Instead of waiting for status confirmation, the controller proactively sends the access command in advance, assuming the memory will be ready by the time data transfer is needed. This eliminates the status checking delay while maintaining operational reliability.
Solution Approach 2:
The invention skips the status read command step entirely in the read operation sequence. By removing this intermediate verification step, the controller rushes through the command issuance process directly to the memory access command, reducing operational time while the memory's internal timing ensures data readiness when required.
2Reliability
If status read commands are issued to check memory plane readiness, then operational reliability is improved, but power consumption increases
Solution Approach 1:
The controller performs preliminary command issuance without waiting for status confirmation, eliminating the need for power-consuming status read commands. By sending the memory access command in advance based on predetermined timing, the controller avoids activating additional circuitry for status monitoring, thereby reducing power consumption.
Solution Approach 2:
The invention extracts and removes the status read command step from the read operation sequence. By taking out this unnecessary verification step, the system eliminates the associated power consumption while maintaining reliability through the memory's inherent timing characteristics and the controller's proactive command issuance.
3Reliability
If traditional read command sequencing is used, then memory operation reliability is maintained, but read operation speed decreases
Solution Approach 1:
The controller issues the memory access command as a preliminary action before the memory plane has officially completed its read operation. By anticipating the memory's readiness based on predetermined timing intervals, the controller overlaps command issuance with memory operation, thereby increasing read speed without compromising data integrity or reliability.
Solution Approach 2:
The invention maintains continuity of useful action by eliminating idle waiting periods. Instead of pausing to check status, the controller continuously progresses through the command sequence, keeping the data bus and control logic actively engaged. This continuous operation increases read speed while the memory's internal timing ensures reliable data transfer when the access command is executed.
Data Source
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AI summary
An operation method of a memory controller (110) includes sequentially transmitting a first read command for the first plane (PLNa) and a second read command for the second plane (PLNb) to the nonvolatile memory device (120), transmitting a first status read command corresponding to the first read command to the nonvolatile memory device (120), transmitting a first memory access command corresponding to the first read command to the nonvolatile memory device (120) based on first status information, receiving first read data that is output from the nonvolatile memory device (120), skipping issuing of a status read command corresponding to the second read command and transmitting a second memory access command corresponding to the second read command to the nonvolatile memory device (120), after receiving the first read data, and receiving second read data that is output from the nonvolatile memory device (120).