Memory Controller Pre-fetching Pixel Data for Power Saving

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Solution Overview

Problem

Existing display systems face challenges in reducing power consumption, particularly in battery-powered devices, due to the high power consumption of main memory used for storing pixel data, which is not fully utilized during idle times or when displaying static images.

Innovation Solution

An integrated circuit with a memory controller that pre-fetches pixel data from a high-power external memory into a lower-power internal memory, allowing the external memory to enter a power-saving mode, and streams the data to the display module at a lower data rate, while using the internal memory as a cache during active modes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If pixel data is continuously streamed from external memory to display module, then display refresh is maintained, but power consumption increases

Engineering Contradiction:

Improvepower consumptionVSAvoiddata streaming rate

Core Design Contradiction:

Use of energy by moving objectVSSpeed

Solution Approach 1:

The system pre-fetches pixel data from external memory into internal memory before the display module needs it. The memory controller proactively transfers data during periods when the display is refreshing, so that when the display needs data, it is already available in internal memory, allowing external memory to enter low-power mode.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

Internal memory acts as an intermediary buffer between external memory and the display module. It decouples the high-speed data transfer requirements from the low-power operational requirements, allowing external memory to operate at high speed only when necessary to fill internal memory, then switch to low-power mode.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Duration of action of moving object

If external memory operates continuously, then pixel data availability is ensured, but battery life decreases

Engineering Contradiction:

Improvebattery lifeVSAvoidpixel data availability

Core Design Contradiction:

Duration of action of moving objectVSReliability

Solution Approach 1:

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The display refresh operation provides continuous useful action that consumes power, while the patent introduces periods where external memory operation is suspended. By synchronizing data transfer with display refresh cycles and using internal memory as a buffer, the system maintains continuous display functionality while creating idle periods for external memory to enter low-power states.

Inventive Principle:

Principle #20Continuity of useful action

3Speed

If internal memory is used as cache during active mode, then data access speed improves, but device complexity increases

Engineering Contradiction:

Improvedata access speedVSAvoidmemory management complexity

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

The internal memory serves multiple functions: it acts as a cache for the processor during active modes, as a frame buffer for the display controller, and as a temporary storage to decouple high-speed data transfer from low-power operation. This multi-functionality reduces the need for separate dedicated memory structures for each purpose.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The system dynamically reconfigures the memory architecture based on operational mode. During active modes, internal memory is coupled to both the processor and display controller for high-speed access. During low-power modes, the coupling is reconfigured to allow external memory to enter low-power state while maintaining display functionality through internal memory.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS8810589B1Method and apparatus for refreshing display

Publication Date: 2014.08.19 MARVELL ISRAEL (M L S L) LTD

AI summary

Aspects of the disclosure provide an integrated circuit. The integrated circuit includes a first memory, a memory controller, and a display controller coupled to a display module. The memory controller is selectively coupled to the first memory and to a second memory that has higher power consumption than the first memory. The second memory includes a frame buffer storing pixel data of images to be displayed on the display module. When the integrated circuit enters a power saving mode, the memory controller, while coupled to the first memory and the second memory, pre-fetches pixel data of an image from the second memory into the first memory at a first data rate. Further, when the integrated circuit is in the power saving mode, the display controller streams the pixel data from the first memory to the display module at a second data rate that is lower than the first data rate, and the second memory is configured into a memory power-saving mode after the pre-fetching until the second memory is accessed for additional pixel data.