Memory Controller Queue Routing for Parallel Die Commands

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Solution Overview

Problem

Existing memory systems face challenges in efficiently distributing commands to multiple memory dies in parallel, leading to issues such as head of line blocking and increased memory requirements for queue management.

Innovation Solution

A memory system with a controller that utilizes a first and second command queue for each memory die, allowing commands to be efficiently distributed and managed, reducing the need for multiple queues per submission queue and minimizing memory usage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple submission queues are provided in the host to enable parallel command distribution, then command distribution efficiency is improved, but memory requirements for queue management increase

Engineering Contradiction:
Improvecommand distribution efficiencyVSAvoidmemory requirements
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The patent merges multiple submission queue management functions into a unified controller architecture. The controller consolidates the management of multiple SQs and distributes commands to multiple memory dies, reducing the total memory required for queue management while maintaining parallel processing capability. This is achieved by implementing a centralized command distribution mechanism that shares memory resources across multiple queues.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The controller is designed with multi-functional capabilities to manage multiple submission queues and distribute commands to multiple memory dies simultaneously. This universal design allows the same memory resources to be shared across different queue management functions, reducing overall memory requirements while maintaining high command distribution efficiency.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Speed

If commands are distributed to multiple memory dies in parallel, then processing speed is improved, but head of line blocking occurs

Engineering Contradiction:
Improveprocessing speedVSAvoidhead of line blocking
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent segments the command distribution into multiple independent paths by providing multiple submission queues, each capable of independent command issuance. This segmentation allows different command streams to be processed in parallel across multiple memory dies, preventing head of line blocking where one slow command would delay others. Each queue can be independently managed and distributed to appropriate memory dies.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The controller implements dynamic command distribution that adapts to the processing status of different memory dies. When certain memory dies are busy or experiencing delays, the controller dynamically redirects commands to available dies, maintaining optimal processing speed and preventing head of line blocking effects from propagating through the entire system.

Inventive Principle:
Principle #15Dynamics

3Device complexity

If a simple queue management structure is used, then device complexity is reduced, but command distribution efficiency decreases

Engineering Contradiction:
Improvequeue management structureVSAvoidcommand distribution efficiency
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent introduces a multi-dimensional queue management structure with two levels: submission queues in the host and command queues in the controller. This dimensional expansion allows efficient command distribution without requiring complex management logic at each level. The separation of concerns between host-side submission queues and controller-side command queues simplifies the overall structure while maintaining high distribution efficiency.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS20260010470A1Memory system and method
Publication Date: 2026.01.08 KIOXIA CORP
  • US20260010470A1 patent drawing
  • US20260010470A1 patent drawing
  • US20260010470A1 patent drawing

AI summary

A memory system includes a non-volatile memory including one memory die; and a controller coupled to the non-volatile memory and a host including a plurality of submission queues. The controller includes a first command queue corresponding to the memory die and a second command queue corresponding to the memory die. The controller is configured to: retrieve a first command from a first one of the submission queues; determine whether a second command retrieved from the first submission queue before the first command is retrieved is stored in the second command queue; when the second command is stored in the second command queue, store the first command retrieved from the first submission queue in the first command queue; and when the second command is not stored in the second command queue, store the first command retrieved from the first submission queue in the second command queue.