Memory Controller Defect Detection in Row Lines
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Solution Overview
Problem
Semiconductor memory devices experience reliability issues due to resistive defects in row lines other than word lines, leading to increased read latency and uncorrectable errors.
Innovation Solution
A data storage device with a memory controller that checks for resistive defects in row lines other than word lines and manages affected memory blocks as bad blocks, or adjusts program operation times to mitigate defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the memory controller uses a standard program operation time for all memory blocks, then the operation is simple and fast, but resistive defects in row lines cause increased read latency and uncorrectable errors
Solution Approach 1:
The memory controller performs a preliminary check during the program operation to detect resistive defects in row lines before they cause read errors. By checking whether the program operation is successfully completed and detecting resistive defects early, the system prevents future read latency issues without requiring complex post-manufacturing testing
Solution Approach 2:
The system dynamically adjusts the program operation time based on detected resistive defects. When a resistive defect is detected in a specific memory block, the controller extends the program operation time for that block beyond the standard duration. This dynamic adjustment ensures reliable programming of affected blocks while maintaining standard operation times for normal blocks, balancing reliability with operational efficiency
2Reliability
If the program operation time is extended for memory blocks with resistive defects, then programming reliability improves, but the overall operation time increases
Solution Approach 1:
The system applies different program operation times to different memory blocks based on their specific conditions. Memory blocks with detected resistive defects receive extended program operation times, while normal blocks use the standard program operation time. This localized adjustment ensures that only affected blocks consume additional time, minimizing the overall time loss while maintaining programming reliability for defective blocks
Data Source
AI summary
A data storage device including: a memory device including a plurality of memory blocks; and a memory controller configured to control the memory device, wherein the plurality of memory blocks are connected with row lines, wherein the row lines include word lines, wherein the memory controller is further configured to: check whether a resistive defect occurs at the row lines except for the word lines; and set a program operation time of a memory block corresponding to a row line, at which the resistive defect occurs, to be longer than a program operation time of the other memory blocks.