Memory Controller Selective Error Correction
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Solution Overview
Problem
Memory controller circuits face challenges in cost and power consumption due to the need for large memory and increased power usage from implementing error-correcting code (ECC) techniques, especially in cost-constrained applications where error detection and correction are required to handle errors in data read from memory devices.
Innovation Solution
A memory controller circuit that selectively generates and stores error-correction information based on the criticality of user inputs, using a command processor to determine whether error-correction information is needed, and storing it in a memory circuit, thereby optimizing memory usage and power consumption by only generating ECC for critical data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ECC technique is implemented to perform error detection and correction on read data, then data integrity is improved, but memory storage requirements and power consumption increase
Solution Approach 1:
The patent applies local quality by differentiating between critical and non-critical data inputs. Error correction information is selectively generated and stored only for critical data that requires high reliability, while non-critical data is stored without additional error correction overhead. This selective approach optimizes memory usage by allocating error correction resources locally to only those data elements that truly need them.
Solution Approach 2:
The patent implements partial action by generating error correction information for only a subset of data inputs rather than all data. The command processor determines which inputs are critical and require error correction, applying ECC selectively rather than universally. This partial application of error correction reduces the overall memory storage burden while maintaining data integrity for critical operations.
2Reliability
If ECC technique is implemented for error detection and correction, then data reliability is improved, but power consumption increases
Solution Approach 1:
The patent applies local quality to power consumption by enabling error correction functionality only when processing critical data inputs. The command processor identifies critical inputs and activates ECC generation and storage only for those cases, leaving non-critical data processing to consume minimal power. This localized activation of error correction significantly reduces overall power consumption compared to continuous ECC operation.
Solution Approach 2:
The patent implements partial action regarding power usage by performing error correction operations only partially - specifically, only for critical data inputs rather than all inputs. The command processor selectively triggers ECC generation based on input criticality, resulting in partial execution of power-intensive error correction operations and corresponding reduction in overall power consumption.
3Reliability
If ECC technique is implemented to ensure data integrity, then error correction capability is improved, but device complexity and PCB size increase
Solution Approach 1:
The patent applies local quality by concentrating error correction functionality within the memory controller circuit rather than distributing it across the entire PCB. The command processor and error correction logic are integrated into the memory controller, eliminating the need for separate external error correction circuits and reducing overall PCB footprint. Error correction is applied locally to critical data paths without requiring system-wide complexity.
Solution Approach 2:
The patent merges the error correction functionality with the memory controller circuit. The command processor that manages memory operations also determines criticality of inputs and triggers error correction. The error correction logic is combined with the memory interface and control logic, creating an integrated solution that reduces device complexity and PCB size compared to separate error correction modules.
Data Source
AI summary
A memory controller circuit is disclosed. The memory controller circuit is coupled to an external memory device. The memory controller circuit selectively generates error-correction information for a user input. The selection is based on whether the user input is one of predefined inputs. In order to facilitate that, the memory controller circuit includes a command processor circuit and a memory circuit. The error-correction information is stored within the memory circuit located within the memory controller circuit. Selectively generating the error-free correction information may significantly reduce the amount of memory storage that is required within the memory controller circuit.