Memory Controller Skew Control for Multi-Rank DDR Synchronization
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Solution Overview
Problem
As memory speeds increase, existing skew control methods become inadequate in ensuring simultaneous arrival of all data bits and their corresponding data strobe signals, especially in multi-rank memory configurations where each bit may be provided by multiple memory sources, leading to significant skew differential issues.
Innovation Solution
A memory controller system that determines the optimum delay for each data bit by testing each rank and calculating an average delay to deskew the signals, minimizing circuitry requirements and achieving optimal synchronization across multiple memory ranks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional deskew methods are used with selectable delays for each data bit and data strobe, then skew compensation is achieved, but significant space is required on the memory controller
Solution Approach 1:
The patent merges the deskew functionality for multiple ranks into a unified delay structure. Instead of implementing separate selectable delay circuits for each rank, the invention combines them into a single delay structure that serves all ranks, thereby reducing the overall circuitry space while maintaining effective skew compensation across multiple memory ranks.
Solution Approach 2:
The delay structure is designed to be universal and multi-functional, serving multiple memory ranks simultaneously. A single delay circuit implementation handles deskew operations for all ranks, making the circuitry adaptable to different rank configurations without requiring additional dedicated circuits for each rank, thus reducing space complexity.
2Productivity
If memory speeds continue to increase, then data transfer efficiency is improved, but skew differential becomes more significant and existing control methods become inadequate
Solution Approach 1:
The patent implements a dynamic delay adjustment mechanism that can adapt to different memory speeds and rank configurations. The delay structure is designed to be adjustable and flexible, allowing it to maintain accurate synchronization even as memory speeds increase and skew differentials become more significant, thereby preserving reliability at higher productivities.
3Quantity of substance
If a single bit is selectively provided by multiple memory sources in multi-rank configurations, then memory capacity is increased, but skew differential varies depending on which memory provides the bit
Solution Approach 1:
The patent applies local quality by implementing rank-specific delay adjustments within a unified delay structure. Each rank can have its delay independently calibrated to compensate for its specific skew characteristics, while still using the same physical delay circuitry. This allows the system to maintain skew consistency across multiple memory sources without requiring separate delay circuits for each rank.
Data Source
AI summary
A dual data rate (DDR) memory controller and method are provided. The method includes: receiving a first data strobe at a first terminal from a first memory having a first rank; receiving a first data signal at a second terminal from the first memory having the first rank; calibrating the first data signal with the first data strobe to produce a first calibration value; receiving a second data strobe at the first terminal from a second memory having a second rank; receiving a second data signal at the second terminal from the second memory having the second rank; calibrating the second data signal with the second data strobe to produce a second calibration value; determining a final calibration value using the first and second calibration values; and using the final calibration value to time the first data signal and the second data signal during a read operation of the memories.