Memory Controller Test Mode Access via Segmented Paths
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Solution Overview
Problem
During the manufacturing and testing phases of memory sub-systems, accessing memory device test modes is challenging due to incompatibility with existing interface protocols, making failure analysis processes like RMA time-consuming and costly, as data necessary for identifying defective DRAM dies becomes inaccessible.
Innovation Solution
A test mode access component is introduced within the memory sub-system controller, enabling access to memory device test modes through additional data paths that allow non-compliant signaling, allowing data like fuse identification (FID) to be accessed for failure analysis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If memory device test modes are accessed using existing interface protocols, then compatibility with standard protocols is maintained, but access to test mode data becomes impossible
Solution Approach 1:
The interface is segmented into two independent paths: a compliant path for normal operations and a non-compliant test path for accessing test mode data. This allows the system to maintain protocol compliance for standard operations while providing separate access to test mode data through additional data paths that do not require protocol compliance.
Solution Approach 2:
A test mode access component acts as an intermediary between the host system and the memory device test modes. This component enables access to test mode data by bridging the gap between compliant interface protocols and the non-compliant test mode signaling requirements.
2Loss of information
If additional data paths are added for test mode access, then access to previously inaccessible data is enabled, but device complexity increases
Solution Approach 1:
The test mode access functionality is merged with the existing memory sub-system controller rather than being implemented as a separate external device. The test mode access component integrates into the controller architecture, allowing test mode data access to be achieved through existing controller resources and reducing overall system complexity.
Solution Approach 2:
The memory sub-system controller is designed to perform multiple functions: it handles normal data operations through compliant protocols and simultaneously provides test mode data access through non-compliant paths. This multi-functionality eliminates the need for separate dedicated test equipment, reducing device complexity.
3Ease of operation
If non-compliant signaling is used for test mode access, then access to test modes is enabled, but compatibility with existing protocols is lost
Solution Approach 1:
The interface is segmented into two independent paths: a compliant path for normal operations and a non-compliant test path for accessing test mode data. This allows the system to maintain protocol compliance for standard operations while providing separate access to test mode data through additional data paths that do not require protocol compliance.
Solution Approach 2:
A test mode access component acts as an intermediary between the host system and the memory device test modes. This component enables access to test mode data by bridging the gap between compliant interface protocols and the non-compliant test mode signaling requirements.
Data Source
AI summary
A system includes a memory device and a processing device coupled to the memory device. The processing device is configured to switch an operating mode of the memory device between a test mode and a non-test mode. The system further includes a test mode access component that is configured to access the memory device while the memory device is in the test mode to perform a test mode operation.