Memory Controller Timing Delay for Shared Interface Data Collision
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Solution Overview
Problem
Memory systems face data collisions on shared interfaces due to timing differences between memory devices and controllers, leading to bandwidth limitations and potential data loss, which existing solutions attempt to address by using common clock signals, increasing complexity and power consumption.
Innovation Solution
Implementing a system where read commands are delayed by one or more unit time intervals when switching between memory devices to ensure data is placed on the interface at appropriate times, using a buffer memory to store data during delays, and varying the timing of read commands to reduce the need for additional circuitry and pins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a common clock signal is used to synchronize memory devices, then data collisions are avoided, but device complexity and power consumption increase
Solution Approach 1:
The patent extracts the clock signal generation function from the memory device and relocates it to the memory controller. The controller generates clock signals and provides them to memory devices through dedicated clock signal lines, eliminating the need for complex internal clock circuits and multiple pins in the memory device while maintaining synchronization and preventing data collisions.
Solution Approach 2:
The memory controller serves multiple functions: it manages data transfers, generates clock signals for synchronization, and coordinates multiple memory devices. By centralizing control functions in the controller, the patent reduces the functional complexity requirements of individual memory devices while maintaining system-wide coordination and reliability.
2Productivity
If memory access timing is optimized for speed, then bandwidth increases, but timing conflicts on shared interfaces occur
Solution Approach 1:
The patent implements preliminary timing setup by establishing fixed timing relationships between command issuance and data placement. The memory controller pre-determines when data will be placed on the interface based on known memory device access times, allowing optimized high-speed operation while preventing timing conflicts through advance coordination of data placement timing across multiple devices.
3Reliability
If additional circuitry is added to synchronize memory devices, then data collision is prevented, but power consumption increases
Solution Approach 1:
The patent extracts the power-intensive clock signal generation function from the memory device and relocates it to the memory controller. This eliminates the need for memory devices to maintain internal clock circuits and phase-locked loops, significantly reducing their power consumption while the controller provides centralized clock signals through efficient dedicated lines.
Solution Approach 2:
Memory devices use the provided clock signals to self-synchronize their data placement timing without requiring additional active synchronization circuitry. The devices autonomously align their output timing with the controller's clock edges, achieving reliable synchronization with minimal power consumption.
Data Source
AI summary
Embodiments of the present invention provide memory systems having a plurality of memory devices sharing an interface for the transmission of read data. A controller can identify consecutive read requests sent to different memory devices. To avoid data contention on the interface, for example, the controller can be configured to delay the time until read data corresponding to the second read request is placed on the interface.