Memory Core Transposed Matrix Calculation via Mode Switching
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Solution Overview
Problem
Current semiconductor apparatuses face challenges in performing fast and accurate transposed matrix calculations, which are essential for data processing in applications like synthetic aperture radars and UAVs, due to the massive data volumes and real-time processing requirements.
Innovation Solution
A semiconductor apparatus with a memory core that includes a switching circuit allowing mode switching between two operation modes, enabling efficient data input/output operations between unit memory regions and a data I/O circuit, facilitating transposed matrix calculations by controlling transistor operations based on signal line levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a conventional memory core structure is used, then the device complexity is low, but the speed of transposed matrix calculation is insufficient
Solution Approach 1:
The patent implements dynamic mode switching between first and second operation modes through a switching circuit controlled by a mode selection signal. In the first mode, the first transistor is controlled by the first signal line level while the second transistor is turned off. In the second mode, the second transistor is controlled by the second signal line level while the first transistor is turned off. This dynamic reconfiguration enables the memory core to adapt its access pattern for transposed matrix calculations, significantly improving calculation speed without requiring a completely new hardware architecture.
Solution Approach 2:
The memory core is designed with dual-transistor unit cells that can operate in multiple modes. The same physical structure (unit cell with first and second transistors) serves both conventional read/write operations and transposed matrix calculation operations. This multi-functionality allows the system to perform transposed matrix calculations efficiently without adding separate dedicated hardware, thus improving speed while controlling device complexity.
2Productivity
If mode switching capability is added to the memory core, then the productivity of transposed matrix calculation is improved, but the device complexity increases
Solution Approach 1:
The patent merges the mode switching function directly into the unit cell structure itself. The switching circuit is integrated with the first and second transistors, and the mode selection signal directly controls the transistor operation states. This merging of functions at the unit cell level enables high productivity for transposed matrix calculations while minimizing the increase in device complexity, as the switching capability is embedded rather than added as a separate complex subsystem.
3Adaptability or versatility
If the memory core uses fixed operation mode, then the ease of operation is high, but the adaptability for different calculation types is low
Solution Approach 1:
The memory core employs dynamic mode switching controlled by a mode selection signal that can be easily adjusted based on calculation requirements. The switching circuit responds to the mode selection signal to reconfigure transistor control connections, enabling the system to adapt between conventional operations and transposed matrix calculations. This dynamic adaptability is achieved through simple signal-based control rather than complex reconfiguration mechanisms, maintaining ease of operation while significantly improving versatility.
Data Source
AI summary
A memory core includes a first signal line; a second signal line; a first transistor coupled between the second signal line and a data storage element; a second transistor coupled between the first signal line and the data storage element; and a switching circuit configured to, in response to a mode selection signal, switch an operation of the memory core between a first mode and a second mode, the first mode controlling the first transistor according to a level of the first signal line and turning off the second transistor and a second mode controlling the second transistor according to a level of the second signal line and turning off the first transistor.