Memory Device Current Limiter with Adaptive Bias
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Solution Overview
Problem
Conventional current limiters for RRAM memory devices, especially those using cascode transistor structures, suffer from increased voltage overhead and area overhead due to temperature fluctuations and manufacturing variability, which affect the operation voltage and chip area usage.
Innovation Solution
A closed-loop bias generator is used in conjunction with a current limiter circuit that includes a cascode structure with a global bottom transistor and column select transistors acting as the top transistor, providing adaptive bias voltage adjustment to stabilize operation voltage and reduce overhead, while using a single bottom transistor for all columns to minimize area usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If cascode transistor structures are used in conventional current limiters, then current limiting function is achieved, but voltage overhead increases and area overhead increases
Solution Approach 1:
The current limiter is divided into column-specific top transistors (column select transistors) and a shared global bottom transistor. This segmentation allows each column to have its own current limiting capability while sharing the voltage overhead burden, reducing overall voltage overhead per column operation.
Solution Approach 2:
The global bottom transistor serves as a shared resource for all columns, providing current limiting functionality across multiple columns simultaneously. This multi-functionality reduces the total number of transistors needed, thereby reducing area overhead while maintaining current limiting reliability.
2Reliability
If cascode transistor structures are used in conventional current limiters, then current limiting function is achieved, but area overhead increases
Solution Approach 1:
The current limiter architecture segments functionality between column-specific top transistors and a shared global bottom transistor. This segmentation reduces redundant transistor instances, minimizing the total area required for current limiting circuits across all columns.
Solution Approach 2:
The global bottom transistor is designed to serve multiple columns universally, eliminating the need for separate bottom transistors for each column. This universal design significantly reduces area overhead while maintaining reliable current limiting through the shared device.
3Reliability
If conventional current limiters are used, then current limiting is provided, but operation voltage becomes unstable due to temperature fluctuations and manufacturing variability
Solution Approach 1:
A bias generator circuit provides adaptive bias voltage to the global bottom transistor, creating a feedback mechanism that compensates for temperature fluctuations and manufacturing variability. This feedback control stabilizes the operation voltage of the current limiter across varying conditions while maintaining reliable current limiting.
Data Source
AI summary
A memory device includes a memory array including a plurality of memory cells arranged in rows and columns. A closed loop bias generator is configured to output a column select signal to the memory array. A current limiter receives an output of the closed loop bias generator. The current limiter is coupled to a plurality of the columns of the memory array.