3D Memory Cell Dam Structure for Moisture and Crack Isolation
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Solution Overview
Problem
Existing three-dimensional semiconductor memory devices face challenges in preventing moisture penetration and crack propagation, which affect their electrical performance and reliability.
Innovation Solution
A semiconductor memory device is designed with a dam structure and dam isolation insulating layers surrounding the memory cell array and peripheral circuit, using alternating semiconductor layers and isolation layers to create a protective barrier against moisture and cracks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a three-dimensional semiconductor memory device is designed with stacked memory cells to increase capacity, then memory capacity is improved, but the device becomes more susceptible to moisture penetration and crack propagation
Solution Approach 1:
The device is divided into multiple functional layers including cell array region, scribe lane region, dam structure, and isolation insulating layers. This segmentation creates distinct zones that can independently address different functional requirements, including protection against moisture and cracks while maintaining high memory capacity through the stacked cell structure
Solution Approach 2:
The dam isolation insulating layer and second dam isolation insulating layer serve as intermediary protective structures between the memory cell array and the external environment. These isolation layers act as barriers that prevent moisture penetration and crack propagation while allowing the memory cell stack to maintain its high-capacity three-dimensional structure
2Reliability
If isolation structures are added to prevent moisture penetration and crack propagation, then reliability is improved, but device complexity increases
Solution Approach 1:
The dam structure combines multiple functions into a single integrated component: it provides mechanical support for the stacked memory cells, creates isolation regions for moisture protection, and defines the boundaries between cell array and scribe lane regions. This merging reduces overall device complexity compared to implementing separate structures for each function
Solution Approach 2:
The dam isolation insulating layer and second dam isolation insulating layer serve multiple purposes simultaneously: they provide electrical isolation between different regions, act as physical barriers against moisture penetration, prevent crack propagation, and support the mechanical structure of the stacked memory cells. This multi-functionality reduces the need for additional specialized components
Data Source
AI summary
Provided is a semiconductor memory device including: a first substrate comprising a cell array region and a first scribe lane region surrounding the cell array region in a plan view; a memory cell array on the cell array region; a dam structure on the first scribe lane region, the dam structure surrounding the memory cell array in a plan view and the dam structure comprising a first sidewall facing the memory cell array and a second sidewall opposite the first sidewall; a first dam isolation insulating layer between the memory cell array and the first sidewall; a second dam isolation insulating layer on the second sidewall; and a dummy stack on the first scribe lane region of the first substrate, the dummy stack comprising a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked in a vertical direction.