Memory Data Input Circuit Test Control for Stacked Packages
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Solution Overview
Problem
The challenge in testing semiconductor memory devices with a stacked or System-In-Package structure is the limited accessibility of test pads, making it difficult to perform direct testing due to their small size and limited number, which hinders efficient testing and evaluation, especially for operations like Error Correction Code (ECC) operations.
Innovation Solution
A memory device with a data input circuit and test control circuit that allows for the selection and control of data input circuits based on test mode information, enabling the transmission of test data through a limited number of test pads to corresponding channels, and the ability to copy and set data in diverse patterns for comprehensive testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a stacked or System-In-Package structure is used to increase integration and performance, then the number of semiconductor memory chips that can be integrated is improved, but the accessibility of test pads deteriorates, making direct testing difficult
Solution Approach 1:
The patent introduces an additional test data input pad as an intermediary access point. This extra pad serves as a mediator that allows test equipment to access internal test data without requiring direct access to the buried pads of the stacked or SIP structure, thus resolving the contradiction between high integration and test accessibility
Solution Approach 2:
The additional test data input pad is designed to serve multiple functions: it can receive test data from test equipment, route it through data input circuits to various channels, and support different test modes (including ECC operation testing). This multi-functionality allows a single pad to address multiple testing requirements in the integrated device
2Device complexity
If the number of test pads is limited to minimize device complexity, then device complexity is reduced, but test coverage and accuracy deteriorate
Solution Approach 1:
The patent implements dynamic control of data input circuits through a test control circuit that selects which circuits to activate based on test mode information. This dynamic selection allows the limited test pads to be flexibly allocated to different testing objectives (e.g., ECC operation testing vs. other functions), maximizing test coverage without requiring additional physical pads
Solution Approach 2:
The data input circuits are segmented into multiple independent circuits corresponding to different channels. The test control circuit can selectively activate specific segments (circuits) based on the test mode, allowing comprehensive testing of different functions through a limited number of test pads by dividing the testing workload across separate circuit segments
Data Source
AI summary
A memory device includes a plurality of data input pads and at least one test data input pad. The memory device also includes a plurality of data input circuits corresponding to a plurality of channels, respectively, the plurality of data input circuits suitable for transmitting respective data received through the data input pads to the corresponding channels. The memory device further includes a test control circuit suitable for selecting at least one data input circuit among the plurality of data input circuits based on test mode information and suitable for controlling the selected data input circuit to transmit set data to the corresponding channel, during a test operation.