Dual-Sided Memory Data Line Layout for Lower RC Delay
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Solution Overview
Problem
In memory devices, the resistance (R) and capacitance (C) of data lines lead to high RC delay, which hinders memory operation speed, especially as the number of memory cells increases, and existing approaches struggle to optimize metal track arrangements for reduced latency and area savings.
Innovation Solution
The use of back side conductive metal lines with larger widths to reduce resistance and capacitance in memory segments, coupled with dual-sided data lines and optimized layout configurations, such as reducing spacing between memory segments and removing assistant circuits, to enhance signal transmission speed and area efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data lines are used to connect memory segments to I/O circuit, then signal transmission is enabled, but RC delay increases which hinders memory operation speed
Solution Approach 1:
The patent introduces a third dimension by routing data lines through both the front side and back side of the substrate. This vertical dimensionality change allows data lines to be separated into two pairs (front side and back side), reducing the length and RC delay of individual lines while maintaining connectivity between memory segments and I/O circuits.
Solution Approach 2:
The data transmission path is segmented into multiple routes by using both front side and back side data lines. This segmentation divides the original single long data line into shorter segments, reducing the overall RC delay and improving signal transmission speed.
2Speed
If metal track arrangement is optimized for reduced latency, then signal transmission speed improves, but area utilization becomes more constrained
Solution Approach 1:
By utilizing the back side of the substrate for additional data lines, the invention extends the routing space into the vertical dimension. This allows for optimized signal paths without increasing the planar footprint, thereby reducing latency while maintaining compact area utilization.
3Area of stationary object
If spacing between memory segments is reduced, then area efficiency improves, but manufacturing precision requirements increase
Solution Approach 1:
The invention reduces the need for lateral spacing between memory segments by utilizing the vertical dimension (back side routing) for data line connections. This allows memory segments to be placed closer together in the planar view, improving area efficiency while the back side routing handles the connection complexity.
4Area of stationary object
If assistant circuits are removed, then area savings are achieved, but device complexity must be managed
Solution Approach 1:
The invention merges the functionality of multiple assistant circuits into the dual-sided data line structure. By using both front side and back side data lines, the system consolidates routing functions that would otherwise require separate assistant circuits, reducing area while managing complexity through integration.
Data Source
AI summary
A memory device in an integrated circuit is provided, including an input/output (I/O) circuit, a first memory segment and a second memory segment that separated from the first memory segment in a first direction, a first pair of data lines on a first side of the integrated circuit, extending in the first direction and configured to couple the first memory segment to the I/O circuit, and a second pair of data lines separated from the first pair of data lines in a second direction, different from the first direction, on a second side, opposite to the first side, of the integrated circuit, and configured to couple the second memory segment to the I/O circuit. A first width of the first pair of data lines is different from a second width of the second pair of data lines.