Memory Address Decoder Fault Injection Detection
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Solution Overview
Problem
Existing methods for detecting fault injection attacks in secure integrated circuit chips are complex and inefficient, requiring additional components and timing signals, and often fail to accurately identify the compromised level of the decoding path.
Innovation Solution
A memory system with multiple stages in the decoding path and integrated fault detecting logic that generates feedback signals to detect faults and trigger an alarm, eliminating the need for external ROM and simplifying the detection process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If external ROM and timing signals are used for fault detection, then detection capability is provided, but device complexity increases
Solution Approach 1:
The patent extracts the fault detection function from external ROM and timing signal mechanisms, and integrates it directly into the address decoder circuit. The decoder generates its own internal feedback signals that indicate faults in the decoding path, eliminating the need for external ROM and complex timing signal coordination.
Solution Approach 2:
The address decoder performs self-diagnosis by generating internal feedback signals that indicate faults in its own decoding path. The decoder monitors its own operation and provides fault information without requiring external detection mechanisms, making the system self-sufficient for fault detection.
2Reliability
If multiple latches and timing signals are added for ROM-based detection, then fault detection is enabled, but ease of operation deteriorates
Solution Approach 1:
The patent removes the complex timing signal generation and coordination requirements by extracting the detection function from the ROM-based system. The new internal feedback mechanism operates automatically with the decoding process without requiring separate timing signals or manual latch control.
Solution Approach 2:
The address decoder incorporates feedback logic that automatically monitors its own decoding operations and generates signals indicating faults in the decoding path. This feedback mechanism operates continuously without requiring external timing signals or manual intervention, simplifying operation while maintaining detection accuracy.
Data Source
AI summary
A memory device, memory address decoder, a memory system and related method for memory attack detection are disclosed. An apparatus includes a memory decoder include multiple stages in a decoding path configured to generate a select signal from an input address signal, and fault detecting logic operably coupled with the memory decoder and configured to receive feedback signals distributed from the multiple stages indicative of a fault along the decoding path.