Nonvolatile Memory Decoder Voltage Segmentation
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Solution Overview
Problem
In nonvolatile semiconductor memory devices, the use of high withstand voltage circuits for both column and row decoders slows down the reading of information from memory cells due to thick gate insulation in high voltage transistors, making it difficult to read data at high speeds.
Innovation Solution
The implementation of a nonvolatile semiconductor memory device with a low voltage circuit for the column decoder and high voltage circuits for specific decoders, allowing for high-speed operation of selecting transistors by using thin gate insulation in low voltage circuits and thick insulation in high voltage circuits, enabling faster read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high withstand voltage circuits are used for both column and row decoders, then sufficient voltage tolerance is achieved, but reading speed decreases due to thick gate insulation in high voltage transistors
Solution Approach 1:
The patent applies different voltage circuit types to different decoder locations: low voltage circuits with thin gate insulation are used for column decoders that require high speed operation, while high voltage circuits with thick gate insulation are used for row decoders that require high voltage tolerance. This local differentiation resolves the contradiction by optimizing each decoder's gate insulation thickness according to its specific functional requirements rather than using a uniform design throughout the system.
2Reliability
If thick gate insulation is used in high voltage transistors, then voltage tolerance is improved, but transistor switching speed deteriorates
Solution Approach 1:
The patent implements local quality by assigning different gate insulation thicknesses to transistors based on their operational requirements: column decoder transistors use thin gate insulation for high-speed switching, while row decoder transistors use thick gate insulation for high voltage tolerance. This spatial differentiation of gate insulation quality allows the system to simultaneously achieve both high speed and high voltage tolerance in appropriate locations.
Solution Approach 2:
The patent segments the decoder system into distinct low voltage and high voltage circuit regions, with column decoders implemented as low voltage circuits and row decoders implemented as high voltage circuits. This segmentation allows independent optimization of gate insulation thickness in each segment, resolving the contradiction between voltage tolerance and switching speed by treating them as separate design concerns in separate system segments.
Data Source
AI summary
A nonvolatile semiconductor memory including a memory cell array of memory cells arranged in a matrix, each of which includes a selective transistor and a memory cell transistor; the first column decoder for controlling the potentials of the bit lines and the source lines; the first row decoder for controlling the potential of the first word lines; the second row decoder for controlling the potential of the second word lines; and the second column decoder. The first column decoder includes a circuit whose withstand voltage is lower than the first row decoder and the second column decoder, and the second row decoder includes a circuit whose withstand voltage is lower than the first row decoder and the second column decoder.