Memory Delay Trimming Self-Calibration for Flash Setup-Hold Precision
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Solution Overview
Problem
Existing flash memory devices face challenges in achieving precise setup/hold times due to variations in doping levels and material differences among memory devices, making nominal delay times insufficient for all devices.
Innovation Solution
A memory delay trimming apparatus with input timing self-calibration, featuring a controller that programs individual delay circuits based on self-calibration methods to achieve zero setup/hold times for each data latch, rather than relying on nominal trim values for all devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If nominal delay times are used for all memory devices, then manufacturing complexity is reduced, but manufacturing precision deteriorates due to device variations
Solution Approach 1:
The patent divides the delay trimming process into two segments: a nominal delay trim applied to all devices during manufacturing, and an additional device-specific trim value determined through self-calibration. This segmentation allows the majority of devices to use the simple nominal value while providing precise customization for individual devices when needed.
Solution Approach 2:
The memory device performs self-calibration by automatically determining its own specific delay trim value through internal testing and measurement. The device uses its own resources (test circuits, controllers) to identify the optimal delay timing without requiring external intervention, thereby achieving precise delay calibration while maintaining ease of manufacture.
2Manufacturing precision
If device-specific delay trimming is implemented, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent combines the delay trimming functionality with existing test circuits and controllers already present in the memory device. The self-calibration process reuses existing infrastructure rather than adding completely separate trimming circuits, thereby achieving device-specific delay precision while minimizing the increase in overall device complexity.
Solution Approach 2:
The test circuits and controllers designed for other purposes (such as device characterization and testing) are made multi-functional by also using them for delay trim determination. This universality allows the same hardware to serve multiple functions, reducing the need for additional dedicated trimming circuitry.
3Reliability
If self-calibration is performed for each device, then reliability is improved by accommodating device variations, but productivity decreases due to additional calibration steps
Solution Approach 1:
The patent implements partial self-calibration where only the necessary portion of devices undergo the full calibration process. Devices that meet nominal specifications can use default trim values, while only those exhibiting timing issues undergo comprehensive self-calibration. This partial action approach maintains high reliability for critical devices while preserving manufacturing throughput.
Solution Approach 2:
The nominal delay trim is applied to all devices in advance during manufacturing before individual self-calibration. This preliminary action ensures that most devices are already properly configured, and only a subset requires additional calibration steps, thereby minimizing the impact on manufacturing productivity while ensuring reliability.
Data Source
AI summary
Methods for memory input timing self-calibration, apparatuses for input timing self-calibration, and systems are disclosed. One such method includes sequentially programming a plurality of delay trim settings into a delay circuit of a data path. The data path can include a data latch coupled to the delay circuit. A clock is coupled to the data latch to clock data into the data latch. Transitions of the data are substantially aligned with transitions of the clock. An output of the data latch is read after each delay trim setting is programmed. A boundary is determined between a first output state of the data latch and a second output state of the data latch wherein the boundary is associated with a particular delay trim setting of the plurality of delay trim settings. The particular delay trim setting is programmed into the delay circuit.