Memory Device Bit-Line Loop Testing for Short and Open Circuits
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Solution Overview
Problem
The increasing complexity of integrated circuits leads to longer testing times and higher costs, with high failure rates and low yield rates during bit line testing, indicating defects in the wafer fabrication process, necessitating improved test efficiency.
Innovation Solution
A method for testing memory devices by measuring resistance and current/voltage values in conductive loops formed by bit lines, identifying short circuits or open circuits through specific test patterns, and evaluating reliability using a flow chart and electronic design automation system.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple test methods are implemented to improve test efficiency, then testing time increases, but testing cost increases significantly
Solution Approach 1:
The patent divides the testing process into multiple test methods (first test method for bit line continuity, second test method for word line continuity, third test method for conductive loop resistance). Each test method targets specific defect types and uses different measurement approaches, allowing comprehensive testing without requiring all methods to be applied to every test point, thus improving overall test efficiency while managing time consumption
Solution Approach 2:
The patent performs preliminary testing at the wafer level before final chip assembly and shipment. By identifying and isolating defective units during wafer testing, the system prevents defective chips from progressing through subsequent manufacturing steps, reducing rework and improving yield. This preliminary action approach allows for more efficient resource allocation and reduces the need for extensive post-manufacturing testing
2Reliability
If comprehensive testing is performed to improve reliability, then testing cost increases, but yield rate decreases
Solution Approach 1:
The patent applies different testing methods and measurement criteria to different regions and types of conductive loops within the memory device. For example, bit line loops use continuity testing while word line loops use resistance measurement. This localized testing approach ensures that each component is tested with the most appropriate method, improving defect detection accuracy without uniformly increasing testing cost across the entire production batch
Solution Approach 2:
The patent implements a feedback mechanism where test results are used to identify and isolate defective units, and this information feeds back into the manufacturing process. By tracking defect patterns and locations, the system can adjust manufacturing parameters and focus testing resources on high-risk areas, improving overall yield while maintaining high reliability through targeted rather than comprehensive testing
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances test efficiency by accurately identifying defects in bit lines, improving yield and reducing production costs by predicting and screening out failed memory devices before shipment.
Implementation Method 1
measuring resistance and current/voltage values in conductive loops formed by bit lines
Data Source
AI summary
A method is provided, including following operations: activating a first word line to couple a first bit line with a second bit line to form a first conductive loop through a first transistor having a first terminal coupled to the first bit line and a second transistor having a first terminal coupled to the second bit line, wherein second terminals of the first and second transistors are coupled together; activating a second word line to couple a third bit line with a fourth bit line to form a second conductive loop, wherein the first and second word lines are disposed below the first to fourth bit lines; and identifying that the first conductive loop, the second conductive loop, or the combinations thereof is short-circuited or open-circuited.