Memory Device Boundary Region Reduction via Unified Contact Formation
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Solution Overview
Problem
The existing design of magnetic memory devices includes large boundary regions between the cell array and peripheral circuits, which increase manufacturing costs and reduce the number of chips that can be produced from a wafer, due to the need for different etching processes and mask arrangements for contact formation in these regions.
Innovation Solution
The proposed memory device structure reduces the boundary region width by forming contacts in the same process steps, eliminating the need for separate mask arrangements and etching steps, allowing for more efficient alignment and formation of contacts across the cell array and peripheral circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If separate etching processes and mask arrangements are used for contact formation in boundary regions, then manufacturing precision is maintained, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent merges the contact formation process for the cell array and peripheral circuits into a single unified process. By designing the mask pattern to cover both regions simultaneously and using a single etching step, the patent eliminates the need for separate processing steps while maintaining alignment accuracy through the shared mask arrangement.
Solution Approach 2:
The mask pattern is designed to serve multiple functions: it defines contact holes for both the cell array region and the peripheral circuit region in the same layer, and it enables simultaneous etching of both regions. This universal mask design eliminates the need for separate mask arrangements and reduces process complexity.
2Manufacturing precision
If larger boundary regions are provided between cell array and peripheral circuits, then manufacturing precision is improved, but productivity decreases
Solution Approach 1:
The patent merges the contact formation operations for adjacent regions into a single process step, allowing tighter spacing between the cell array and peripheral circuits. This eliminates the need for large buffer zones that would be required if separate processes were used, thereby increasing the number of chips that can be manufactured from each wafer.
3Manufacturing precision
If separate mask arrangements are used for different regions, then manufacturing precision is maintained, but loss of time increases
Solution Approach 1:
The patent combines multiple mask application and etching operations into a single unified process. By using one mask pattern that covers both the cell array and peripheral circuit regions, and performing a single etching step, the patent eliminates the sequential time required for separate mask arrangements and multiple etching cycles, thereby reducing the overall manufacturing cycle time.
Data Source
AI summary
A memory device according to embodiments includes a cell array region. The cell array region comprises a plurality of transistors sharing a word line, a plurality of memory elements, and a plurality of first contacts configured to connect the plurality of transistors with the plurality of memory elements, respectively, and aligned with a pitch. The memory device further comprises a second contact positioned at the pitch, along an extension of a row of the plurality of first contacts, outside the cell array region, and configured to be in contact with the word line.