Memory Device Conductive Pillar Bit Lines
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Solution Overview
Problem
Conventional non-volatile memory devices face challenges such as short channel effects, high resistance values in buried bit lines, and complex manufacturing processes, which affect device integrity and performance.
Innovation Solution
A memory device with conductive layers as local bit lines, a composite dielectric layer including a charge trapping layer, and dopant diffusion regions in the substrate, which reduces short channel effects and minimizes device size while increasing operation speed by using a simplified manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the depth of the buried bit lines is decreased to prevent short channel effect, then the short channel effect is reduced, but the resistance values of the buried bit lines become too high
Solution Approach 1:
The patent transitions from traditional buried bit lines to vertical conductive pillars, changing the dimensional orientation of the conductive path. This vertical structure allows the bit lines to extend downward into the substrate rather than being confined to a shallow horizontal plane, thereby reducing resistance without exacerbating short channel effects.
Solution Approach 2:
The conductive pillars are formed using composite material structures, combining different materials with complementary properties. The patent employs a core-shell structure where a conductive core material provides low resistance, while a surrounding dielectric or insulating shell prevents short channel effects and isolates adjacent structures.
2Ease of manufacture
If conventional manufacturing processes are used to form silicon oxide layers and remove silicon nitride, then the memory device can be manufactured, but defects are caused and the procedure becomes complex
Solution Approach 1:
The patent extracts and eliminates the problematic silicon nitride layer formation and removal steps from the manufacturing process. By replacing this with a direct deposition of the conductive pillar structure using atomic layer deposition (ALD), the complex sequence of forming silicon nitride, depositing silicon oxide, and performing CMP or lift-off is completely removed, simplifying the process while improving device integrity.
Solution Approach 2:
The patent replaces mechanical removal processes (CMP - chemical mechanical polishing, or lift-off) with a controlled deposition process using atomic layer deposition (ALD). This substitution eliminates the need for mechanical or chemical removal steps that cause defects, replacing them with a precise, defect-free deposition method that directly forms the desired structure.
3Ease of operation
If gates are formed as block structures from stripe structures, then word lines can connect gate structures, but bridging and short circuit occur if etching is incomplete
Solution Approach 1:
The patent introduces an intermediary material layer (such as a dielectric spacer or insulating layer) between the conductive pillars and the gate structures. This intermediary prevents direct contact that would cause short circuits, while still allowing the word lines to electrically connect to the gate structures through controlled pathways, thus eliminating bridging issues.
Solution Approach 2:
The patent segments the gate structures into discrete, isolated units with clear dielectric separation between them. Rather than forming continuous block structures that require complete etching, the gates are segmented into individual regions that are electrically isolated, preventing bridging and short circuit even if etching is not perfectly complete.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces short channel effects, minimizes memory device size, and enhances operation speed by using conductive layers as local bit lines and a composite dielectric layer for charge trapping, thereby improving device integrity and performance.
Implementation Method 1
the composite dielectric layer includes a charge trapping layer
Implementation Method 2
dopant diffusion regions in the substrate
Data Source
AI summary
A memory device including a substrate, a plurality of conductive layers, a composite dielectric layer and a plurality of gates are provided. Wherein, the conductive layers are disposed on the substrate. The composite dielectric layer is disposed on the substrate and covers the conductive layers. The composite dielectric layer includes a charge trapping layer. The gates are disposed on the composite dielectric layer and across the conductive layers. Wherein, the conductive layers can be used as local bit lines to reduce the resistance values and improve the performance of the memory device.