Semiconductor Memory Device Conductor Layer Doping
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Solution Overview
Problem
In semiconductor memory devices, the existing technologies face challenges in preventing undesirable etching of conductor layers during wet etching processes, which can lead to reduced quality of memory pillars and deterioration of select gate line cut-off characteristics due to phosphorus diffusion.
Innovation Solution
Doping the conductor layer with arsenic, phosphorus, carbon, or boron creates an ion-implanted region that reduces contact resistance and prevents phosphorus diffusion, thereby enhancing the etching resistance and maintaining the integrity of memory pillars and select gate lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the conductor layer is doped with phosphorus to reduce contact resistance, then the contact resistance decreases and cell current flow improves, but phosphorus diffusion occurs during wet etching which deteriorates select gate line cut-off characteristics
Solution Approach 1:
A protective film is introduced as an intermediary layer between the phosphorus-doped conductor layer and the wet etching solution. This protective film prevents phosphorus from diffusing into the wet etching solution while allowing the wet etching process to proceed normally on other structures. The protective film thus mediates between the need for phosphorus doping and the need to prevent phosphorus diffusion.
Solution Approach 2:
The protective film is formed on the conductor layer before the wet etching process begins. This preliminary action prevents phosphorus diffusion from occurring in the first place by creating a barrier that blocks the interaction between phosphorus and the wet etching solution, thereby preventing the harmful effect before it can manifest.
2Ease of manufacture
If wet etching is performed to remove sacrificial layers, then the sacrificial layers are effectively removed, but undesirable etching of the conductor layer occurs which reduces memory pillar quality
Solution Approach 1:
The protective film serves as an intermediary barrier that distinguishes between the conductor layer and the wet etching solution. It allows the wet etching process to effectively remove sacrificial layers while preventing the conductor layer from being undesirably etched, thus maintaining manufacturing precision during the ease of manufacture process.
Solution Approach 2:
The protective film is selectively formed only on regions where conductor layers are present, while leaving other areas exposed to wet etching. This local application of protection ensures that sacrificial layers are removed where needed while conductor layers are protected only where required, achieving both ease of manufacture and manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the risk of unnecessary etching and improves the cell current flow into memory pillars, resulting in a high-quality semiconductor memory device with improved performance.
Implementation Method 1
Doping the conductor layer with arsenic, phosphorus, carbon, or boron creates an ion-implanted region that reduces contact resistance
Implementation Method 2
prevents phosphorus diffusion, thereby enhancing the etching resistance and maintaining the integrity of memory pillars and select gate lines
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes a semiconductor substrate; a first conductor layer provided above the semiconductor substrate and including silicon; a plurality of second conductor layers provided above first conductor layer and stacked apart from each other in the first direction; and a first pillar extending in the first direction through the second conductor layers and including intersection portions where the first pillar intersects the second conductor layer, the intersection portions each functioning as a memory cell transistor, wherein the first conductor layer includes a first region which is in contact with the first pillar and includes at least one element of arsenic (As), phosphorus (P), carbon (C), or boron (B).