Memory Device Etch Methods Using Hard Mask and CF4 CHF3 Chemistry

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Solution Overview

Problem

Conventional etch methods for semiconductor devices face challenges in achieving small design features due to the limitations of photoresist materials, which become too thin and fail to sustain resistance during the etching process, leading to over-etching and improper formation of design features.

Innovation Solution

The use of a hard mask layer and adjusted etch chemistry, including combinations of tetrafluoromethane (CF4), trifluoromethane (CHF3), and oxygen, with specific flow rate ratios and oxygen flow rates, to etch memory device layers, allowing for precise control over critical dimensions as small as 45 nanometers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional photoresist materials are used to define design features, then the etching process can be performed, but the photoresist layer becomes too thin to sustain resistance, resulting in over-etching and improper formation of design features

Engineering Contradiction:
Improvecritical dimension controlVSAvoidphotoresist mask sustainability
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The patent divides the masking function into multiple layers: a photoresist layer for initial patterning and a separate hard mask layer for etching protection. This segmentation allows each layer to perform its specialized function optimally - the photoresist defines the pattern while the harder, more erosion-resistant hard mask sustains the etching process, preventing over-etching and maintaining critical dimension control

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The hard mask layer is formed and patterned before the actual etching process begins. This preliminary action creates a robust protective mask that is specifically designed to withstand the etching plasma, ensuring that the subsequent etching process maintains precision without degrading the mask material

Inventive Principle:
Principle #10Preliminary action

2Length of moving object

If the size and geometry of design features are reduced below critical dimension, then high density memory requirements are met, but conventional photoresist materials become too thin to sustain resistance during etching

Engineering Contradiction:
Improvedesign feature sizeVSAvoidetching accuracy
Core Design Contradiction:
Length of moving objectVSManufacturing precision

Solution Approach 1:

The patent changes the material parameters of the mask layer by introducing a hard mask layer with superior erosion resistance compared to conventional photoresist. This parameter change enables the process to maintain etching accuracy even when design feature sizes are reduced below traditional critical dimensions, as the hard mask's enhanced durability compensates for the smaller feature geometry

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables the fabrication of memory cells with precise critical dimensions, improving control and reducing over-etching issues compared to conventional methods, while maintaining high manufacturing throughput.

Implementation Method 1

providing an etch chemistry comprising tetrafluoromethane (CF4), trifluoromethane (CHF3), and oxygen (O2) to etch at least the control gate layer

Methodology Applied
Scientific EffectPlasma etching: Plasma

Implementation Method 2

The etch process may include an etch chemistry having tetrafluoromethane (CF4), trifluoromethane (CHF3), and at least one of octafluorocyclobutane (C4F8), hexafluorobutadiene (C4F6), or octafluorocyclopentene (C5F8)

Methodology Applied
Scientific EffectChemical reactions: Chemical Bonding

Data Source

PatentUS7972951B2Memory device etch methods
Publication Date: 2011.07.05 SPANSION LLC
  • US7972951B2 patent drawing
  • US7972951B2 patent drawing
  • US7972951B2 patent drawing

AI summary

A method of manufacturing a memory device forms a first dielectric layer over a substrate, forms a charge storage layer over the first dielectric layer, forms a second dielectric layer over the charge storage layer, and forms a control gate layer over the second dielectric layer. The method also forms a hard mask layer over the control gate layer, forms a bottom anti-reflective coating (BARC) layer over the hard mask layer, and provides an etch chemistry that includes tetrafluoromethane (CF4) and trifluoromethane (CHF3) to etch at least the control gate layer.