Semiconductor Memory Device Etch Stop Layer Segmentation
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Solution Overview
Problem
Three-dimensional semiconductor memory devices face process failures due to the formation of memory cell arrays on substrates with peripheral circuits, leading to increased failure rates and reduced reliability.
Innovation Solution
The semiconductor memory device incorporates a substrate with a peripheral circuit, an interconnection array, and a stack structure comprising gate electrodes and sacrificial layers, with a slit between the cell and dummy stack structures to reduce etch stop layer failures and enhance line arrangement density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory cell arrays are formed on substrates with peripheral circuits in three-dimensional semiconductor memory devices, then device integration is achieved, but process failures occur leading to increased failure rates
Solution Approach 1:
The patent divides the memory device into distinct functional regions: a first region containing the peripheral circuit and a second region containing the memory cell array. This spatial segmentation isolates the memory formation processes from the peripheral circuit, preventing process failures in the memory region from affecting the peripheral circuit and thereby reducing overall device failure rates while maintaining integration.
Solution Approach 2:
The patent extracts the memory cell array formation process from the peripheral circuit region by positioning the memory cell array in a separate second region. This extraction allows independent optimization and processing of the memory region without compromising the peripheral circuit, thus improving reliability while achieving device integration.
2Manufacturing precision
If etch stop layers are used in the stack structure, then etch process stability is improved, but punch failures may still occur
Solution Approach 1:
The patent applies different material compositions to different regions of the etch stop layer. The first etch stop layer in the peripheral circuit region has a different composition ratio than the second etch stop layer in the memory cell array region. This local quality differentiation allows each region to have etch stop properties optimized for its specific processing conditions, improving overall etch stability while preventing punch failures through localized material optimization.
Solution Approach 2:
The patent changes the compositional parameters of the etch stop layers between different regions. By adjusting the composition ratio of the etch stop layers to differ between the peripheral circuit region and memory cell array region, the etching characteristics are optimized for each region, thereby improving etch process stability and reducing punch failures.
3Productivity
If line arrangement density is increased, then device functionality is enhanced, but process complexity increases
Solution Approach 1:
The patent segments the device into a first region for peripheral circuits and a second region for memory cell arrays. This segmentation allows independent design and optimization of line arrangements in each region, enabling high line arrangement density in the memory region without unnecessarily complicating the peripheral circuit region, thus enhancing functionality while managing process complexity.
Data Source
AI summary
A semiconductor memory device includes a substrate including a peripheral circuit; an interconnection array disposed on the peripheral circuit; a cell stack structure disposed on the interconnection array, the cell stack structure including gate electrodes stacked in a vertical direction to form a cell step structure; and a dummy stack structure disposed on the interconnection array, the dummy stack structure including sacrificial layers stacked in the vertical direction to form a dummy step structure parallel to the cell step structure. The interconnection array includes a first lower conductive pattern including a center region overlapping with a slit between the cell step structure and the dummy step structure, a first region extending to overlap with the dummy step structure from the center region, and a second region extending to overlap with the cell step structure from the center region.