Non-volatile Memory Device Vertical Pass Transistor Stacking
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Solution Overview
Problem
As memory devices become more integrated and capacitive, the increased number of word lines stacked vertically leads to a larger chip size due to the increased number of pass transistors, complicating the operation and wiring structure, and making it challenging to maintain a compact design.
Innovation Solution
The implementation of a memory device with a cell over periphery (COP) structure, where the pass transistor circuit is arranged in a stair area of the word lines, allowing for vertical pass transistors to be integrated without increasing the chip size, by stacking the memory cell array and pass transistors in a vertical direction and arranging the peripheral circuits in a way that reduces the horizontal area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of word lines stacked vertically is increased to increase integration, then memory capacity is improved, but the number of pass transistors increases causing chip size to increase
Solution Approach 1:
The patent transitions from a planar arrangement of pass transistors to a vertical three-dimensional structure. Pass transistors are stacked above the memory cell array, utilizing the vertical dimension to accommodate additional transistors without expanding the horizontal chip footprint. This dimensional change allows increased integration while maintaining compact chip size.
Solution Approach 2:
The patent implements a nested structure where pass transistors are positioned above and connected to the memory cell array. The control circuit is further nested above the pass transistors, creating a vertical stacking arrangement similar to nested dolls. This nesting enables multiple functional layers to coexist within the same horizontal area, increasing integration without chip size expansion.
2Quantity of substance
If the number of pass transistors is increased to support more word lines, then memory capacity is improved, but the wiring structure becomes complicated
Solution Approach 1:
The patent moves the pass transistor connections from a two-dimensional planar wiring layout to a three-dimensional vertical arrangement. Word lines extend vertically to connect to pass transistors stacked above, and control signals are routed through vertical connections. This vertical dimensionality reduces the horizontal wiring complexity and enables more compact signal routing paths.
Solution Approach 2:
The patent segments the memory device into distinct vertical layers: the memory cell array at the bottom, pass transistors in the middle layer, and control circuits at the top. Each layer performs specific functions and connects to adjacent layers through controlled vertical interconnections. This segmentation organizes the complex wiring into manageable modular sections, simplifying the overall wiring structure.
3Quantity of substance
If pass transistors are arranged in a stair area of word lines with vertical stacking, then integration is enhanced, but the peripheral circuit area is reduced
Solution Approach 1:
The patent utilizes the vertical dimension to stack pass transistors above the memory cell array in the stair area, allowing peripheral circuit functionality to be achieved without consuming additional horizontal area. The control circuit is similarly stacked vertically, enabling high integration while maintaining compact peripheral circuit footprint.
Data Source
AI summary
A memory device including: a memory cell array disposed in a first semiconductor layer, the memory cell array including a plurality of wordlines extended in a first direction and stacked in a second direction substantially perpendicular to the first direction; and a plurality of pass transistors disposed in the first semiconductor layer, wherein a first pass transistor of the plurality of pass transistors is disposed between a first signal line of a plurality of signal lines and a first wordline of the plurality of wordlines, and wherein the plurality of signal lines are arranged at the same level as a common source line.