Non-volatile Memory Device Program Disturbance Control
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Solution Overview
Problem
Semiconductor memory devices face issues with program disturbance and read disturbance phenomena during operations, leading to increased operation time and power consumption.
Innovation Solution
The semiconductor memory device employs a peripheral circuit with a voltage generating unit and control logic that alternately performs program and verification operations by applying specific voltages to word lines, including a second pass voltage to unselected word lines adjacent to the selected word line, which is lower than the first pass voltage applied to other unselected word lines, to prevent channel potential discharge and leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional program operation is performed with uniform pass voltage on all unselected word lines, then the programming process is simple, but program disturbance occurs due to channel potential discharge and leakage current
Solution Approach 1:
The patent applies different pass voltages to different groups of unselected word lines based on their proximity to the selected word line. Specifically, a first pass voltage is applied to unselected word lines adjacent to the selected word line, while a second pass voltage is applied to other unselected word lines. This local differentiation prevents channel potential discharge and leakage current in critical areas without unnecessarily increasing complexity throughout the entire device.
Solution Approach 2:
The patent segments the unselected word lines into two distinct groups: those adjacent to the selected word line and those that are not. This segmentation allows for differentiated voltage control strategies for each group, enabling targeted disturbance prevention while maintaining simpler control for the majority of word lines.
2Productivity
If discharge operations are inserted between program and verification operations, then voltage control is simplified, but operation time increases
Solution Approach 1:
The patent eliminates discharge operations between program and verification steps, allowing the verification operation to proceed continuously. The control logic directly transitions from applying the program voltage to applying the verification voltage without intermediate discharge phases, thereby maintaining continuous useful action and reducing overall operation time.
3Reliability
If verification operation is performed before program operation, then disturbance is reduced, but the verification process becomes less reliable due to potential voltage instability
Solution Approach 1:
The patent applies the verification operation after the program operation is completed. By performing verification after programming, the system ensures that the memory cells have stabilized and the voltage conditions are reliable before checking the programmed data, thereby ensuring verification reliability.
Data Source
AI summary
Provided herein are semiconductor memory devices and operating methods thereof. A semiconductor memory device may include a memory cell array including a plurality of cell strings, and a peripheral circuit. The peripheral circuit may include a voltage generating unit configured to perform a program loop for alternately performing a program operation and a verification operation on the memory cell array. The peripheral circuit may include a control logic configured to control the voltage generating unit to perform the program loop. Wherein, in performing the program loop, a second pass voltage applied to an unselected word line adjacent to a selected word line among a plurality of word lines connected with the memory cell array is lower than a first pass voltage applied to a remaining unselected word line during the program operation.