Semiconductor Memory Device Segmentation for Integration
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Solution Overview
Problem
The integration of semiconductor memory devices is hindered by the technical difficulty of applying a uniform design rule to all components, leading to increased costs and reduced reliability due to the wiring rearranging process required for stacking memory devices, which compromises yield.
Innovation Solution
A memory device configuration featuring a separate input/output circuit chip and core chip, where the input/output circuit chip performs data exchange functions with an external device, allowing for different design rules to be applied to each component, thereby reducing the number of bonding wires and improving reliability and integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a uniform design rule is applied to all components of a semiconductor memory device, then manufacturing consistency is improved, but integration density deteriorates due to the inability to optimize different components for their specific functions
Solution Approach 1:
The semiconductor memory device is divided into multiple independent chips: a first chip containing memory elements and a peripheral circuit, and a second chip containing input/output circuits. This segmentation allows each chip to be designed and manufactured with optimized design rules suitable for its specific function, thereby improving integration density while maintaining manufacturing precision for each component type.
Solution Approach 2:
Different design rules are applied to different components based on their specific requirements. The memory element chip uses design rules optimized for high-density storage, while the input/output circuit chip uses design rules optimized for signal processing and external communication. This local optimization enables higher overall integration density without compromising manufacturing precision for either component type.
2Quantity of substance
If a wiring rearranging process is used to stack memory devices, then integration is improved, but cost increases and reliability decreases
Solution Approach 1:
By segmenting the memory device into separate functional chips (memory element chip and input/output circuit chip), the patent enables direct stacking of these chips without requiring complex wiring rearrangement processes. Each chip maintains its original wiring configuration, eliminating the need for post-stack wiring modifications and thereby improving reliability while achieving integration through the stacking architecture itself.
Solution Approach 2:
The input/output circuits are pre-configured on a separate chip during manufacturing, with their wiring and connections optimized for their specific functions. This preliminary configuration allows the chips to be stacked directly without requiring subsequent wiring rearrangement, thus maintaining both high integration density and high reliability.
3Quantity of substance
If memory devices are stacked using traditional methods, then integration density is improved, but the number of bonding wires increases leading to higher cost and lower yield
Solution Approach 1:
The segmentation of functionality into separate chips (memory elements on one chip, input/output circuits on another) allows for optimized bonding wire configurations. Each chip interface requires bonding wires only for the specific signals needed at that interface, rather than requiring all possible connections to be routed through multiple stacked layers, thereby reducing overall bonding wire complexity.
Solution Approach 2:
By moving the input/output circuits to a separate chip that can be stacked vertically, the patent reduces the horizontal wiring complexity. The bonding wires are concentrated at the interfaces between stacked chips rather than being distributed across multiple layers, simplifying the overall bonding structure and improving yield.
Data Source
AI summary
A memory device is provided. The memory device includes a first semiconductor chip including a memory element and a peripheral circuit configured to write or read data in or from the memory element; and a second semiconductor chip configured to perform an input/output function of data or signals exchanged between an external device and the first semiconductor chip.