Memory Device Self-Testing via On-The-Fly Pattern Generation
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Solution Overview
Problem
Existing semiconductor memory device test devices struggle to keep pace with the high-speed production of semiconductor memory devices, particularly due to economic issues and the need for efficient testing methods.
Innovation Solution
A memory device and test system that includes a memory cell array, timing circuits for generating clock signals, a command decoder for On-The-Fly (OTF) data, a receiver for sampling input data, a deserializer for generating deserialized signals, a data pattern generator for creating pattern signals, and a decoder for transmitting these signals to the memory cell array, allowing for efficient testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional test devices are used to test semiconductor memory devices, then the testing process is simple and straightforward, but the test devices cannot keep pace with high-speed production due to economic constraints and efficiency limitations
Solution Approach 1:
The memory device is designed to perform both normal memory operations and self-testing functions through a unified structure. The data input/output circuit can operate in either mode depending on control signals, eliminating the need for separate dedicated test equipment and enabling the memory device to test itself, thereby achieving high-speed testing without increasing external device complexity
Solution Approach 2:
The memory device performs self-testing by using its own internal resources (memory cell array, data input/output circuit, decoder, serializer/deserializer) to generate test patterns, execute tests, and validate functionality. This self-service capability removes the bottleneck of external test equipment speed limitations and enables testing to keep pace with high-speed production
2Productivity
If high-speed production of semiconductor memory devices is implemented, then productivity increases, but test devices cannot maintain the same speed due to economic and technical constraints
Solution Approach 1:
The self-testing mechanism allows testing to be performed continuously as part of the normal manufacturing flow without requiring separate, time-consuming test cycles. The data input/output circuit can seamlessly transition between normal operation and test modes, maintaining continuous productive action and eliminating idle testing time that would otherwise bottleneck high-speed production
Solution Approach 2:
Test patterns are generated preliminarily within the memory device structure itself using the pattern generator functionality integrated into the data input/output circuit. This preliminary preparation of test data within the device eliminates the need for external test equipment to generate and transmit test patterns, reducing testing time and enabling synchronization with high-speed production rates
Data Source
AI summary
A memory device according to an embodiment includes a memory cell array; a timing circuit configured to generate a first clock signal and a second clock signal, the second clock signal having a frequency that is i-times the frequency of the first clock signal; a command decoder configured to receive On-The-Fly (OTF) data including a plurality of OTF bits; a receiver configured to receive input data, sample the input data based on the first clock signal, and generate a first signal based on the sampled input data; a deserializer configured to generate a first deserialized signal from the first signal based on the second clock signal; a data pattern generator configured to generate a pattern signal based on the first deserialized signal and the OTF data based on the second clock signal; and a decoder configured to transmit the pattern signal to the memory cell array.