3D Memory Device Semiconductor Layer Cross-Section Optimization
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Solution Overview
Problem
In memory devices with three-dimensionally arranged memory cells, increasing the number of electrode layers reduces the cell current flowing through the semiconductor layer, affecting memory capacity and performance.
Innovation Solution
The memory device incorporates a conductive layer, multiple electrode layers, a semiconductor layer that pierces these layers, and an insulating film structure, where the semiconductor base is connected to the semiconductor layer and pierces the second electrode layer, with specific width and spacing configurations to maintain or enhance cell current, including the use of insulating films and semiconductor layers to reduce channel resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of electrode layers is increased to increase memory capacity, then the memory capacity is improved, but the cell current flowing through the semiconductor layer decreases
Solution Approach 1:
The patent applies local quality by creating a semiconductor layer with non-uniform cross-sectional area along its length. The semiconductor layer has a larger cross-sectional area at certain positions (such as at the ends or intermediate positions) compared to other positions. This local expansion of the semiconductor layer reduces channel resistance at critical locations without increasing the overall number of electrode layers, thereby maintaining cell current while supporting increased memory capacity through the stacked structure.
Solution Approach 2:
The patent transitions from a two-dimensional planar structure to a three-dimensional stacked structure by arranging multiple electrode layers and semiconductor layers vertically. This dimensional change allows memory capacity to be increased by adding more layers in the vertical direction rather than expanding horizontally, while the semiconductor layer's cross-sectional area is optimized at different vertical positions to maintain adequate cell current flow through the stacked structure.
2Quantity of substance
If multiple electrode layers are stacked to increase memory capacity, then the memory capacity is improved, but the channel resistance increases causing cell current to decrease
Solution Approach 1:
The patent addresses channel resistance by implementing local quality variations in the semiconductor layer's cross-sectional area. By expanding the semiconductor layer's cross-sectional area at specific positions (such as at the ends or intermediate positions between electrode layers), the channel resistance is reduced locally at these critical points. This allows the device to support multiple electrode layers for increased memory capacity while maintaining adequate current flow by reducing resistance at key locations along the vertical channel.
Solution Approach 2:
The patent applies parameter changes by varying the cross-sectional area parameter of the semiconductor layer along its length. Instead of maintaining a uniform cross-sectional area, the semiconductor layer's cross-sectional area is changed at different positions to optimize electrical characteristics. This parameter variation allows the device to achieve lower channel resistance in the vertical channel formed by multiple electrode layers, thereby maintaining cell current while supporting increased memory capacity through the stacked architecture.
Data Source
AI summary
A memory device includes a conductive layer, a plurality of first electrode layers, a first semiconductor layer extending through the plurality of first electrode layers in a first direction toward the plurality of first electrode layers from the conductive layer, a first insulating film including a tunneling insulator film, a charge-trapping film and a blocking insulator film, a second electrode layer, and a semiconductor base. The charge-trapping film is spaced along the first direction from the semiconductor base, a distance in the first direction between the charge-trapping film and the semiconductor base is larger than a thickness of the blocking insulator film in a second direction toward the plurality of first electrode layers from the first semiconductor layer.