Memory Device Stepped Gate Electrodes and Trench Segmentation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing memory devices face challenges in increasing memory capacity and reliability due to delamination issues between the interlayer insulating layer and signal lines during manufacturing, which affects the erase characteristics and overall reliability of the device.
Innovation Solution
A memory device design that includes a substrate with a cell array region and a connection region, featuring a gate stack with gate electrode layers of varying lengths forming a stepped structure, and an interlayer insulating layer divided into regions by first and second trenches, with a dummy pattern part between contact plugs to prevent delamination and stress-related defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the interlayer insulating layer is made continuous to improve manufacturing simplicity, then the ease of manufacture is improved, but delamination occurs between the interlayer insulating layer and signal lines during manufacturing
Solution Approach 1:
The interlayer insulating layer is divided into multiple separate regions by introducing first trenches and second trenches. These trenches segment the continuous interlayer insulating layer into discrete portions, preventing delamination while maintaining manufacturing feasibility. The segmentation creates isolated insulating regions that reduce stress accumulation and prevent large-scale delamination events.
Solution Approach 2:
Material is removed to form first trenches and second trenches within the interlayer insulating layer. By extracting portions of the interlayer insulating layer, the patent creates a structured configuration that eliminates delamination-prone continuous regions while maintaining the necessary insulating function in critical areas.
2Quantity of substance
If the gate electrode layers are extended by different lengths to form a stepped structure to improve memory capacity, then the quantity of substance is improved, but the device complexity increases
Solution Approach 1:
The gate electrode layers are extended in different lengths along the horizontal dimension, creating a stepped structure. This dimensional variation allows for increased memory capacity by utilizing additional spatial arrangement, while the stepped configuration maintains manufacturing feasibility through systematic layer extension rather than complex three-dimensional structures.
3Reliability
If the first trenches and second trenches are introduced to divide the interlayer insulating layer to prevent delamination to improve reliability, then the reliability is improved, but the manufacturing precision requirements increase
Solution Approach 1:
The interlayer insulating layer is segmented into multiple discrete regions by first trenches and second trenches. This segmentation prevents delamination by creating isolated insulating portions that are less prone to stress-induced separation, thereby improving reliability while maintaining manageable manufacturing precision requirements through systematic trench placement.
Data Source
AI summary
A memory device including a substrate, a plurality of channel columns, a gate stack, an interlayer insulating layer, a plurality of first trenches, and at least one second trench. The substrate includes a cell array region and a connection region. The channel columns cross an upper surface of the substrate in the cell array region. The gate stack includes a plurality of gate electrode layers surrounding the channel columns in the cell array region. The gate electrode layers extend to different lengths in the connection region to form a stepped structure. The interlayer insulating layer is on the gate stack. The first trenches divide the gate stack and the interlayer insulating layer into a plurality of regions. The at least one second trench is inside of the interlayer insulating layer in the connection region and between the first trenches.