Semiconductor Memory Device Temperature Compensation
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Solution Overview
Problem
Conventional NAND-type flash memory devices face challenges in accurately reading data due to temperature-dependent threshold variations, requiring large circuits to generate temperature-characteristic read voltages, which complicates the process and increases circuit scale, especially in multivalue storage systems.
Innovation Solution
A semiconductor memory device design that cancels temperature-dependent threshold changes by varying the voltage applied to the well region and source line, using a sense amp connected to a bit line, and generating temperature-characteristic voltages for the source line and bit line, simplifying the circuit structure and allowing for easier trimming of temperature characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If temperature characteristic is imparted to the selected word line to cancel threshold variation, then reading accuracy is improved, but circuit scale increases and trimming becomes impossible in multivalue systems
Solution Approach 1:
The patent introduces a source line as an intermediary element to apply temperature-compensating voltage, replacing the direct application to word lines. This mediator approach allows temperature compensation to be achieved through voltage variation on the source line rather than through complex word line voltage control circuits, thereby reducing circuit scale while maintaining reading accuracy.
Solution Approach 2:
The patent changes the parameter being controlled from word line voltage to source line voltage. By varying the source line voltage according to temperature characteristics instead of adjusting word line voltages, the system achieves temperature compensation with simpler circuitry. This parameter substitution eliminates the need for complex voltage generation circuits and trimming mechanisms in multivalue memory systems.
2Measurement precision
If temperature characteristic is imparted to the selected word line, then reading accuracy is improved, but the number of required voltage sets and trimming processes increases
Solution Approach 1:
The source line serves as a mediator that simplifies the voltage application process. Instead of requiring multiple voltage sets and trimming processes for word lines, the temperature compensation is achieved through a single source line voltage adjustment, greatly simplifying the manufacturing and calibration process.
Solution Approach 2:
The source line is given a dual function: it serves both as the common source connection for memory cells and as the vehicle for applying temperature-compensating voltage. This multi-functionality eliminates the need for separate voltage adjustment circuits and trimming processes, making the system easier to manufacture and adapt to multivalue storage requirements.
3Device complexity
If constant voltage is applied to the selected word line for reading, then circuit operation is simplified, but temperature-dependent threshold variation causes reading errors
Solution Approach 1:
The source line acts as an intermediary that introduces temperature compensation into the reading process without complicating the word line voltage control. By applying temperature-dependent voltage to the source line rather than the word line, the system maintains simple constant voltage operation on word lines while achieving temperature compensation through the source line mediator.
Solution Approach 2:
The patent changes which parameter is varied with temperature: instead of varying word line voltage to compensate for threshold shifts, the system varies source line voltage. This parameter change allows constant word line voltage operation (simple circuit) while achieving temperature compensation through source line voltage adjustment, resolving the contradiction between operational simplicity and reading accuracy.
Data Source
AI summary
A semiconductor memory device, comprising: a memory cell array of a plurality of memory cell units, each memory cell unit including a plurality of serially connected memory cells formed on the same well region, each memory cell having a floating gate and a control gate stacked, said serially connected memory cells having one end serially connected to a first selection gate transistor, said serially connected memory cells having the other end connected to a common source line via a second selection gate transistor; a sense amp connected to one end of said first selection gate transistor via a bit line and operative to read data out of said memory cell array; and wherein a voltage applied to said well region and said source line varies to cancel a change of threshold of said memory cells depending on the temperature.